Simulation Results

Simulation Results: aes/unmasked

15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: xcelium [unknown]

Coverage statistics

Total
96.17 %

code
93.10 %

assert
98.11 %

func
97.29 %

block
94.11 %

line
95.75 %

branch
87.47 %

toggle
98.08 %

FSM
91.11 %

Validation stages

V1		100.00%
V2		99.54%
V2S		93.67%
V3		10.00%

24/24 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	aes_wake_up	2.000s	63.046us	1	1	100.00
smoke				10	10	100.00
	aes_smoke	3.000s	94.349us	10	10	100.00
csr_hw_reset				1	1	100.00
	aes_csr_hw_reset	2.000s	90.286us	1	1	100.00
csr_rw				5	5	100.00
	aes_csr_rw	2.000s	56.437us	5	5	100.00
csr_bit_bash				1	1	100.00
	aes_csr_bit_bash	8.000s	328.082us	1	1	100.00
csr_aliasing				1	1	100.00
	aes_csr_aliasing	2.000s	108.085us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	aes_csr_mem_rw_with_rand_reset	2.000s	88.094us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	aes_csr_rw	2.000s	56.437us	5	5	100.00
	aes_csr_aliasing	2.000s	108.085us	1	1	100.00

217/218 passed

99.54 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				70	70	100.00
	aes_smoke	3.000s	94.349us	10	10	100.00
	aes_config_error	4.000s	103.012us	50	50	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
key_length				70	70	100.00
	aes_smoke	3.000s	94.349us	10	10	100.00
	aes_config_error	4.000s	103.012us	50	50	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
back2back				35	35	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
	aes_b2b	8.000s	453.846us	25	25	100.00
backpressure				10	10	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
multi_message				94	95	98.95
	aes_smoke	3.000s	94.349us	10	10	100.00
	aes_config_error	4.000s	103.012us	50	50	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
	aes_alert_reset	4.000s	135.285us	24	25	96.00
failure_test				84	85	98.82
	aes_man_cfg_err	3.000s	82.179us	10	10	100.00
	aes_config_error	4.000s	103.012us	50	50	100.00
	aes_alert_reset	4.000s	135.285us	24	25	96.00
trigger_clear_test				10	10	100.00
	aes_clear	4.000s	238.755us	10	10	100.00
nist_test_vectors				1	1	100.00
	aes_nist_vectors	5.000s	178.832us	1	1	100.00
reset_recovery				24	25	96.00
	aes_alert_reset	4.000s	135.285us	24	25	96.00
stress				10	10	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
sideload				20	20	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
	aes_sideload	3.000s	208.386us	10	10	100.00
deinitialization				10	10	100.00
	aes_deinit	3.000s	101.472us	10	10	100.00
stress_all				10	10	100.00
	aes_stress_all	36.000s	1097.016us	10	10	100.00
alert_test				10	10	100.00
	aes_alert_test	2.000s	56.393us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	aes_tl_errors	4.000s	330.920us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	aes_tl_errors	4.000s	330.920us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	aes_csr_hw_reset	2.000s	90.286us	1	1	100.00
	aes_csr_rw	2.000s	56.437us	5	5	100.00
	aes_csr_aliasing	2.000s	108.085us	1	1	100.00
	aes_same_csr_outstanding	3.000s	173.484us	5	5	100.00
tl_d_partial_access				12	12	100.00
	aes_csr_hw_reset	2.000s	90.286us	1	1	100.00
	aes_csr_rw	2.000s	56.437us	5	5	100.00
	aes_csr_aliasing	2.000s	108.085us	1	1	100.00
	aes_same_csr_outstanding	3.000s	173.484us	5	5	100.00

V2S

918/980 passed

93.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reseeding				10	10	100.00
	aes_reseed	5.000s	121.856us	10	10	100.00
fault_inject				611	660	92.58
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
shadow_reg_update_error				18	20	90.00
	aes_shadow_reg_errors	3.000s	85.452us	18	20	90.00
shadow_reg_read_clear_staged_value				18	20	90.00
	aes_shadow_reg_errors	3.000s	85.452us	18	20	90.00
shadow_reg_storage_error				18	20	90.00
	aes_shadow_reg_errors	3.000s	85.452us	18	20	90.00
shadowed_reset_glitch				18	20	90.00
	aes_shadow_reg_errors	3.000s	85.452us	18	20	90.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	aes_shadow_reg_errors_with_csr_rw	4.000s	788.331us	20	20	100.00
tl_intg_err				29	30	96.67
	aes_sec_cm	5.000s	1070.803us	5	5	100.00
	aes_tl_intg_err	4.000s	295.961us	24	25	96.00
sec_cm_bus_integrity				24	25	96.00
	aes_tl_intg_err	4.000s	295.961us	24	25	96.00
sec_cm_lc_escalate_en_intersig_mubi				24	25	96.00
	aes_alert_reset	4.000s	135.285us	24	25	96.00
sec_cm_main_config_shadow				18	20	90.00
	aes_shadow_reg_errors	3.000s	85.452us	18	20	90.00
sec_cm_gcm_config_shadow				18	20	90.00
	aes_shadow_reg_errors	3.000s	85.452us	18	20	90.00
sec_cm_main_config_sparse				135	145	93.10
	aes_smoke	3.000s	94.349us	10	10	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
	aes_alert_reset	4.000s	135.285us	24	25	96.00
	aes_core_fi	245.000s	10008.284us	91	100	91.00
sec_cm_gcm_config_sparse				151	160	94.38
	aes_config_error	4.000s	103.012us	50	50	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
	aes_core_fi	245.000s	10008.284us	91	100	91.00
sec_cm_aux_config_shadow				18	20	90.00
	aes_shadow_reg_errors	3.000s	85.452us	18	20	90.00
sec_cm_aux_config_regwen				20	20	100.00
	aes_readability	3.000s	61.954us	10	10	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
sec_cm_key_sideload				20	20	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
	aes_sideload	3.000s	208.386us	10	10	100.00
sec_cm_key_sw_unreadable				10	10	100.00
	aes_readability	3.000s	61.954us	10	10	100.00
sec_cm_data_reg_sw_unreadable				10	10	100.00
	aes_readability	3.000s	61.954us	10	10	100.00
sec_cm_key_sec_wipe				10	10	100.00
	aes_readability	3.000s	61.954us	10	10	100.00
sec_cm_iv_config_sec_wipe				10	10	100.00
	aes_readability	3.000s	61.954us	10	10	100.00
sec_cm_data_reg_sec_wipe				10	10	100.00
	aes_readability	3.000s	61.954us	10	10	100.00
sec_cm_data_reg_key_sca				10	10	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
sec_cm_key_masking				10	10	100.00
	aes_stress	4.000s	98.292us	10	10	100.00
sec_cm_main_fsm_sparse				10	10	100.00
	aes_fi	4.000s	79.023us	10	10	100.00
sec_cm_main_fsm_redun				636	685	92.85
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	3.000s	272.852us	25	25	100.00
sec_cm_cipher_fsm_sparse				10	10	100.00
	aes_fi	4.000s	79.023us	10	10	100.00
sec_cm_cipher_fsm_redun				611	660	92.58
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
sec_cm_cipher_ctr_redun				322	350	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
sec_cm_ctr_fsm_sparse				10	10	100.00
	aes_fi	4.000s	79.023us	10	10	100.00
sec_cm_ctr_fsm_redun				314	335	93.73
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_ctr_fi	3.000s	272.852us	25	25	100.00
sec_cm_ghash_fsm_sparse				10	10	100.00
	aes_fi	4.000s	79.023us	10	10	100.00
sec_cm_ctrl_sparse				636	685	92.85
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	3.000s	272.852us	25	25	100.00
sec_cm_main_fsm_global_esc				24	25	96.00
	aes_alert_reset	4.000s	135.285us	24	25	96.00
sec_cm_main_fsm_local_esc				636	685	92.85
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	3.000s	272.852us	25	25	100.00
sec_cm_cipher_fsm_local_esc				636	685	92.85
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	3.000s	272.852us	25	25	100.00
sec_cm_ctr_fsm_local_esc				314	335	93.73
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_ctr_fi	3.000s	272.852us	25	25	100.00
sec_cm_ghash_fsm_local_esc				10	10	100.00
	aes_fi	4.000s	79.023us	10	10	100.00
sec_cm_data_reg_local_esc				611	660	92.58
	aes_fi	4.000s	79.023us	10	10	100.00
	aes_control_fi	61.000s	0.000us	279	300	93.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	aes_stress_all_with_rand_reset	50.000s	8906.138us	1	10	10.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				25 test runs
	aes_cipher_fi	115227319252214007045933759208335522975103188760081802122636283828585833395223	None
	aes_control_fi	64258225448887346173102947037337588429487389726975563865488976632726358924296	None
	aes_cipher_fi	35188056378136949825963229135296647103344173631832843283922284366862308381115	None
	aes_cipher_fi	110274709657019494653540626021837011209774360087636905605485100331888386992867	None
	aes_cipher_fi	101886182411153714302722871580114850430940689382870319576223940269058928239090	None
	aes_cipher_fi	19114552825951912544626304340489873576733691978505636697719267188333464537307	None
	aes_control_fi	58720626332212806187428759433174450083833753320333803317303154707683453148341	None
	aes_cipher_fi	91928881298013984735101200744400857312374645666776042009239934182760643141126	None
	aes_control_fi	50599775926282400045482168559238833313237040090316404848468788651075445785069	None
	aes_control_fi	87134827983201125134114475908727797002018911807854399239039898313512580458850	None
	aes_control_fi	71607956009588256564677261448160362560001529981841693582173656855099793992858	None
	aes_cipher_fi	39364335514202010057998310089855328579075516340466103791427720437802001935942	None
	aes_control_fi	107133249768453912203778638579649424724293150556609635877954227088286900167828	None
	aes_control_fi	86002442538644116661083576511315601940931719453054142938716178894720385555188	None
	aes_cipher_fi	95445409147738686378841831475530416414159067103272238487595725989666393440318	None
	aes_control_fi	44817318173553657645099765425711916914191830797280060336464287269341492001080	None
	aes_cipher_fi	74560037256707702315671974387376133765200269520411743737385934416354775636002	None
	aes_control_fi	68833786053575853211205013206324222489483129125324411751876307026807145735175	None
	aes_control_fi	86047453688191796952016566145924197743233360550701538878722912266276481699705	None
	aes_cipher_fi	52117303719037827533617837812053364888124237748191173433672544524134967558275	None
	aes_control_fi	67391825638594428877451683484803714790815703008014711882201327961118373016590	None
	aes_cipher_fi	43916280522867203147388652885922737634987346434188959834400620525162016554854	None
	aes_control_fi	92737739548119490388790227368094389491422410851523519875826415094971662777096	None
	aes_cipher_fi	10663680541245620546881310432263106069197719337512784473489670839797520723921	None
	aes_cipher_fi	38646523556724219841818595198460399345953497842551703818534733685253025899368	None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!				15 test runs
	aes_cipher_fi	84171949546798935261693428755192335405559198448418019945144730462197575405316	145	UVM_INFO @ 10004015625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	3685536314668855904766224074582414736262835871211428843539188988617135297696	149	UVM_INFO @ 10012163919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	49216600162508113431544181553800802281154475409554524429131987988799164592896	152	UVM_INFO @ 10011303616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	38265461239576081906414505433158425480505593029500691726933760887574469774540	146	UVM_INFO @ 10013036745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	98097478627322910667613913775840952783858815617695955000968161329436375920293	147	UVM_INFO @ 10011978459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	27203590761582552537188887582621792038327106892983837205750744055640374892003	143	UVM_INFO @ 10002456405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	6602330781194754117497220868548646811708536702362043442559598909635279660432	146	UVM_INFO @ 10006624012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	80997338394276037297221241671449099391239612353535528866027457806175381488771	152	UVM_INFO @ 10008032053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	19510522975693286560094547329254913185745945358413986347590414206196650192346	144	UVM_INFO @ 10002397084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	114928480805035629803425432379674334472260421189621643170934401183137229304038	151	UVM_INFO @ 10003934226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	44335293354023663265033899604589447092988755083237865359643215066188169823064	145	UVM_INFO @ 10004726701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	41724835845965319131510909968416041797464789487719807355303262296507438056312	147	UVM_INFO @ 10003287496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	105234025169413328485900049325287271538166523798505862083883105717445673254401	142	UVM_INFO @ 10015373217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	34164048608143528475630971098924032775273669753636232795303970970902180064112	146	UVM_INFO @ 10014066209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	99422547842477849725976363401452441676758824295085211319652780147139295775690	144	UVM_INFO @ 10005069091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!				9 test runs
	aes_control_fi	59663331882607473991603515630613735228755211843312644722420393588665896300942	150	UVM_INFO @ 10006237566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	71093055894005340344070989095177203540596584062722901991796036694240870161752	153	UVM_INFO @ 10008756995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	24736277358139939321724272079558627611467268163941642335428086535887724521736	150	UVM_INFO @ 10007968153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	31580457066676311725663233202240183057114978186535416702406248119633357942882	146	UVM_INFO @ 10006811265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	19527135543809914997452006282529652826250607221266696133119818783964378191761	147	UVM_INFO @ 10003589596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	104367692768332069097447569631822908959489393094475457303377442850923171755788	150	UVM_INFO @ 10024318983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	81906547021686089960054461383021427137910591070851773414683000466655892570384	149	UVM_INFO @ 10003126278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	25655551324292295125217264553942545678224746217099543223896876147851075462954	152	UVM_INFO @ 10013065247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	19917154898162561699706351649138877278978027965488577836105696576015992582994	148	UVM_INFO @ 10006516482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!				6 test runs
	aes_core_fi	76533314115548697137608648498093761969850767523912403261059856998875097638675	142	UVM_INFO @ 10002092329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	114338541912215554507541340419680932311829600657185478085592559308296703818578	156	UVM_INFO @ 10004261562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	16860325271284083874945318202255469268908981689607148419426930690452125543441	144	UVM_INFO @ 10004070161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	65270014329315958015242318530240449174022657393831465398049576483678699370620	139	UVM_INFO @ 10016503696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	108048098492035357505709928530732389254124573344370580732430022081374656676721	140	UVM_INFO @ 10003773394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	89079663777612041440165057025790342652665682098335514581830728278651970625515	151	UVM_INFO @ 10004535004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues				4 test runs
	aes_stress_all_with_rand_reset	84821117256342867503999108732199211117947892137743547403475335068075762090025	2644	UVM_INFO @ 2386210768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	11761693748916213175117131686109615343767875050444591677801527816663498085720	581	UVM_INFO @ 834378928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	10373888678329671919179386522103414560908396514056795579010736904968348520769	1195	UVM_INFO @ 707799682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	105682787391580522527813208105729008772476840330446116008229253753911330623476	1646	UVM_INFO @ 2570365093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	aes_stress_all_with_rand_reset	107139841563112886861375373509967474468024189219910058191843480191519096744399	1438	UVM_INFO @ 2640031895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	109835509571883995041021825648622495839285562087273281655467646947867070681110	159	UVM_INFO @ 117780814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: aes_reg_block_extended.ctrl_shadowed reset value:				2 test runs
	aes_shadow_reg_errors	8534917572263765198562515873133033815780313424980285259283862828954454173304	106	UVM_INFO @ 39095021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_shadow_reg_errors	101958914347710788682991106123494811964251858399152907970868539309254229742712	106	UVM_INFO @ 33830642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				2 test runs
	aes_stress_all_with_rand_reset	73088331268992020269561523419375616579191403065906764262483176158702520948437	2341	UVM_INFO @ 5262728378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	4257147575866202505384347798287673907069351820347963588162168643977506976148	681	UVM_INFO @ 873276665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred!				2 test runs
	aes_core_fi	85181822126719543411636288869111291994245766859287973601348369299344686077156	140	UVM_INFO @ 10027700003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	43832935030055059325322084877611816132957709094062250078278724675126246048310	142	UVM_INFO @ 10008790725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				1 test run
	aes_stress_all_with_rand_reset	83197073016116264344165351771402777592485576125335787524165118499539882605257	222	UVM_INFO @ 361072116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [aes_common_vseq] expect alert:fatal_fault to fire				1 test run
	aes_tl_intg_err	83521755657744735916813545080519953673524985825505581337686697714394613817581	109	UVM_INFO @ 34304637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/reseed_opt/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_/rtl/aes_core.sv,1112): Assertion AesModeValid has failed				1 test run
	aes_alert_reset	95968486761768265514436637143894006245195976099313311693575063656458373845482	726	xmsim: E,ASRTST (/nightly/current_run/scratch/reseed_opt/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 12066155 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed xmsim: E,ASRTST (/nightly/current_run/scratch/reseed_opt/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 12066155 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 12066155 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed UVM_ERROR @ 12066155 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=, Comparison=CompareOpEq, exp_data=, call_count=8)				1 test run
	aes_core_fi	100142451515258794244620257078604109907665188680866887332987694136480523839054	142	UVM_INFO @ 10008283822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---