Simulation Results: clkmgr

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.21 %
  • code
  • 98.91 %
  • assert
  • 95.90 %
  • func
  • 87.82 %
  • line
  • 99.33 %
  • branch
  • 99.16 %
  • cond
  • 96.06 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.070s 54.925us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.960s 45.746us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.230s 22.854us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 7.650s 671.529us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.550s 66.530us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.660s 64.623us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.230s 22.854us 5 5 100.00
clkmgr_csr_aliasing 1.550s 66.530us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.240s 65.829us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.120s 27.041us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.330s 158.286us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.130s 73.752us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.070s 54.925us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 11.340s 2002.034us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 8.170s 1701.607us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 11.340s 2002.034us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 43.040s 4926.383us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.160s 173.701us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 5.130s 1579.925us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 5.130s 1579.925us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 0.960s 45.746us 1 1 100.00
clkmgr_csr_rw 1.230s 22.854us 5 5 100.00
clkmgr_csr_aliasing 1.550s 66.530us 1 1 100.00
clkmgr_same_csr_outstanding 1.350s 57.556us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 0.960s 45.746us 1 1 100.00
clkmgr_csr_rw 1.230s 22.854us 5 5 100.00
clkmgr_csr_aliasing 1.550s 66.530us 1 1 100.00
clkmgr_same_csr_outstanding 1.350s 57.556us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 16 30 53.33
clkmgr_sec_cm 26.620s 10031.646us 2 5 40.00
clkmgr_tl_intg_err 45.820s 10045.843us 14 25 56.00
shadow_reg_update_error 14 20 70.00
clkmgr_shadow_reg_errors 1001.730s 200000.000us 14 20 70.00
shadow_reg_read_clear_staged_value 14 20 70.00
clkmgr_shadow_reg_errors 1001.730s 200000.000us 14 20 70.00
shadow_reg_storage_error 14 20 70.00
clkmgr_shadow_reg_errors 1001.730s 200000.000us 14 20 70.00
shadowed_reset_glitch 14 20 70.00
clkmgr_shadow_reg_errors 1001.730s 200000.000us 14 20 70.00
shadow_reg_update_error_with_csr_rw 12 20 60.00
clkmgr_shadow_reg_errors_with_csr_rw 1036.810s 200000.000us 12 20 60.00
sec_cm_bus_integrity 14 25 56.00
clkmgr_tl_intg_err 45.820s 10045.843us 14 25 56.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 11.340s 2002.034us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 8.170s 1701.607us 10 10 100.00
sec_cm_meas_config_shadow 14 20 70.00
clkmgr_shadow_reg_errors 1001.730s 200000.000us 14 20 70.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.540s 319.548us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.350s 306.906us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.350s 75.846us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 1.150s 42.890us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.210s 50.823us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.230s 22.854us 5 5 100.00
sec_cm_idle_ctr_redun 2 5 40.00
clkmgr_sec_cm 26.620s 10031.646us 2 5 40.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.230s 22.854us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.230s 22.854us 5 5 100.00
prim_count_check 2 5 40.00
clkmgr_sec_cm 26.620s 10031.646us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 5.040s 1147.004us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 223.770s 80344.142us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault 12 test runs
clkmgr_tl_intg_err 85150231223598227415672151797727224241629160718298721819780190130251078435943 118
UVM_INFO @ 10049209049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 83568737204911499447907459544058687751612329284464914970288918636779661457291 92
UVM_INFO @ 10031646386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 114339955602757574759955789450297406918023607995225010192813344222123787024322 133
UVM_INFO @ 10146787776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 30938541438757235669463754707784974198170029402960263300977744822202542339347 111
UVM_INFO @ 10018001578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 41675285945952429040665111055577065560575570971725350258712370542377616883066 131
UVM_INFO @ 10080666010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 71060805531672892022501742461082163606114882424305105242995192755981663247338 124
UVM_INFO @ 10097221110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 64306949711961785391854491129580891660105997843949064871806108882202828560484 159
UVM_INFO @ 10722146917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 39840610681593570273291893930506621568704174270534208290836314115257110528606 138
UVM_INFO @ 10045842967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 39024958878054901127742255473019507094129867046953959889890962217993135539094 136
UVM_INFO @ 10062630671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 41528712183006216434328213139122641285128272647421530603798869507191934163043 182
UVM_INFO @ 10211820248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 15411796383991427212554759252705320466365350958204457275915390898904620353643 155
UVM_INFO @ 10197820028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 112941824520841174814174446824912022315305604184169860859540606163935202021900 114
UVM_INFO @ 10029012802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 9 test runs
clkmgr_shadow_reg_errors 76051970248852195566230300131860034078896148762739211932272358636882797504300 80
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 52938610719923253285178708611295471573573896551309681467402389351870738328636 80
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 84893559536527755811666927839974979601339516948037312449342472293637078503362 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 36715478704572300330654443582214292833239298638373992166295108151891604394161 80
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 86768604679823043788892873685622934542561614973915098871655824825498098234243 80
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 96456412934383199285409086127295316371490682955813934210254050393755108472490 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 68379486997146858046639932729659861697101497281769746218423548615691535489667 80
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 88980841590310609075164318130972180796129899209491453121976169932668428818054 80
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 7946033709911387066181797950970224067143900260147722167986832668402601507860 80
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
clkmgr_sec_cm 51550107038440592328254409196158867063059148437843262886618300714813909155952 84
UVM_INFO @ 11962767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 18363085115365556030908327090455741336120697908654238885188163390104713379877 100
UVM_INFO @ 27342332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 88905031805628186327564449653172462342717341110361615286560341359792504194469 80
UVM_INFO @ 61411366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 69258000601426793321480698592490738723045008760124429652204305314806367768466 81
UVM_INFO @ 197067346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 47785808432060945213002206656626538211016421131376833294723275658332063529389 79
UVM_INFO @ 9450689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 101987329278169483598710410478783143266254722285771977074151974867917829419525 80
UVM_INFO @ 2138201643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 109935080532594616468613221879619493518219611192742423153003595657971711070368 81
UVM_INFO @ 2091162428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 84093880298787688381056209424201448264343495889665693302026173191533799857300 80
UVM_INFO @ 2094196107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---