Simulation Results: csrng

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.08 %
  • code
  • 96.23 %
  • assert
  • 95.85 %
  • func
  • 90.15 %
  • block
  • 98.59 %
  • line
  • 99.57 %
  • branch
  • 96.46 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.01%
V2S
99.77%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 35.000s 85.276us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 35.000s 16.866us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 35.000s 21.258us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 49.000s 360.307us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 38.000s 164.434us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 35.000s 37.896us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 35.000s 21.258us 5 5 100.00
csrng_csr_aliasing 38.000s 164.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 39.000s 130.487us 200 200 100.00
alerts 500 500 100.00
csrng_alert 55.000s 5423.729us 500 500 100.00
err 499 500 99.80
csrng_err 178.000s 10001.256us 499 500 99.80
cmds 1 25 4.00
csrng_cmds 3600.000s 0.000us 1 25 4.00
life cycle 1 25 4.00
csrng_cmds 3600.000s 0.000us 1 25 4.00
stress_all 24 25 96.00
csrng_stress_all 460.000s 20710.040us 24 25 96.00
intr_test 10 10 100.00
csrng_intr_test 35.000s 46.288us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 36.000s 61.001us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 35.000s 108.308us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 35.000s 108.308us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 35.000s 16.866us 1 1 100.00
csrng_csr_rw 35.000s 21.258us 5 5 100.00
csrng_csr_aliasing 38.000s 164.434us 1 1 100.00
csrng_same_csr_outstanding 36.000s 38.718us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 35.000s 16.866us 1 1 100.00
csrng_csr_rw 35.000s 21.258us 5 5 100.00
csrng_csr_aliasing 38.000s 164.434us 1 1 100.00
csrng_same_csr_outstanding 36.000s 38.718us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
csrng_sec_cm 35.000s 201.440us 5 5 100.00
csrng_tl_intg_err 34.000s 126.671us 24 25 96.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 34.000s 39.260us 25 25 100.00
csrng_csr_rw 35.000s 21.258us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 55.000s 5423.729us 500 500 100.00
sec_cm_intersig_mubi 24 25 96.00
csrng_stress_all 460.000s 20710.040us 24 25 96.00
sec_cm_main_sm_fsm_sparse 704 705 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
csrng_sec_cm 35.000s 201.440us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 704 705 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
csrng_sec_cm 35.000s 201.440us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 704 705 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
csrng_sec_cm 35.000s 201.440us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 704 705 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
csrng_sec_cm 35.000s 201.440us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 704 705 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
csrng_sec_cm 35.000s 201.440us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 55.000s 5423.729us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 699 700 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
sec_cm_constants_lc_gated 24 25 96.00
csrng_stress_all 460.000s 20710.040us 24 25 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 55.000s 5423.729us 500 500 100.00
sec_cm_tile_link_bus_integrity 24 25 96.00
csrng_tl_intg_err 34.000s 126.671us 24 25 96.00
sec_cm_aes_cipher_fsm_sparse 704 705 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
csrng_sec_cm 35.000s 201.440us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 699 700 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
sec_cm_aes_cipher_ctrl_sparse 699 700 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
sec_cm_aes_cipher_fsm_local_esc 699 700 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
sec_cm_aes_cipher_ctr_redun 704 705 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
csrng_sec_cm 35.000s 201.440us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 699 700 99.86
csrng_intr 39.000s 130.487us 200 200 100.00
csrng_err 178.000s 10001.256us 499 500 99.80
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 19 test runs
csrng_cmds 11990149315594467832014997415934164248833728040853718304287188770304536178924 130
UVM_INFO @ 141994693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 47848077870854582483106878610897539570165869610101559815804396042827792341798 140
UVM_INFO @ 217142031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 50696301342617125719698572256442501429914305076738001353951666098018099828046 130
UVM_INFO @ 44587995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 92840155956880734203855843085553787583428668900702897413001455850843007280255 130
UVM_INFO @ 295679164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 63646843384049199451237550152961155082277559812606126649843713205590495925679 130
UVM_INFO @ 41542611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 5585036185308894227663041388334800922356145506219793454433343604031386356906 130
UVM_INFO @ 59309149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 79601894212739584733827957466604635520015620281969471501604639887948983077900 140
UVM_INFO @ 114777540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 101117190795106373735725577623436575349388479838142929196690650592279127905614 130
UVM_INFO @ 69184503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 8145447493291236019271812435708210921637694967279181298263081654305336548156 130
UVM_INFO @ 46778651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 61808624757123578181418480787027865922888876005824305197676436538999446524057 130
UVM_INFO @ 76919875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 67993926245654148123484063308590758602279586324103564072029712365440239267078 130
UVM_INFO @ 51412107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 4907344386907862329357963141889420078635313195346781923985497272804812175147 130
UVM_INFO @ 155262341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 25765490525717986142418017881068081269823030646629423783135163978259226764570 130
UVM_INFO @ 60567681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56419963264282951319795914897450943976552124642199131574576998878193151049070 130
UVM_INFO @ 896200468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 42396673861410149488666563176811140833963173355130960978911606913146172188630 130
UVM_INFO @ 253218143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 18803859255288071699913535115371643745963962546930636273136473514927275711077 130
UVM_INFO @ 59906251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 48979372282581832383588408329957833099267084949381189751153064433538740313218 130
UVM_INFO @ 540259203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 81629429501145638289139315820402114366564526518116677243080469583845711838530 130
UVM_INFO @ 7922958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65292248378098528864453201619126695371431386858108314059976729349607811144964 140
UVM_INFO @ 349065965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 12 test runs
csrng_stress_all_with_rand_reset 11081093773633433870298090516032077527466913949725248432062330065980587029724 None
csrng_stress_all_with_rand_reset 93402827048481377060339574790699327536350588542000742058214992751424248345487 None
csrng_stress_all_with_rand_reset 27492335675695121231796294735687806961433196348806565467645254186235732103582 None
csrng_stress_all_with_rand_reset 44725077476925878074965475390062425817543619141369794669000592871660129677243 None
csrng_stress_all_with_rand_reset 23047507513352804367843396191306910817204032886132835186605851308713264585213 None
csrng_stress_all_with_rand_reset 55845175321935831870096883991758529371571439093855316702004435816056466705970 None
csrng_stress_all_with_rand_reset 38686016970129496941769152595552522137975928251469436387389522525755268126889 None
csrng_stress_all_with_rand_reset 54598940942961047925309437062136445689223209796664717069150133615245035605521 None
csrng_stress_all_with_rand_reset 34389797552341723532023574594044227651001874663661784722901096177611861914040 None
csrng_stress_all_with_rand_reset 79517697631846171627576200304328332935029166247273205489063945713737692003836 None
csrng_cmds 67103932160023128079662190511603473325129794522163174146879675381904914876699 None
csrng_cmds 49627780086484537837922070593018373889215633122009359926134401583497620713545 None
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 2 test runs
csrng_cmds 23396536465865624752598642882081546242774387318928144681574605278115360890898 133
UVM_INFO @ 99819328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 96969598564810171614035903071820258110335439450447585343362085862937596117607 133
UVM_INFO @ 249783556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [csrng_common_vseq] expect alert:fatal_alert to fire 1 test run
csrng_tl_intg_err 62202745245629577350856143123501656253253983156382001429879689850882893228301 112
UVM_INFO @ 16658783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all 38590735503857728945796265334248581563732484447953331736567574272483852235203 137
UVM_INFO @ 1511750163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 66255336110668822094867965174828892413703277074585074088782745394934837345111 149
UVM_INFO @ 4809086751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [csrng_err_vseq] wait timeout occurred! 1 test run
csrng_err 15893229335232616470027496987575298665572777482221121965679346576605970071564 129
UVM_INFO @ 10001256143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---