Simulation Results: edn/edn0

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.30 %
  • code
  • 95.63 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
99.34%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.360s 72.987us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.220s 24.718us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.450s 46.129us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.980s 367.613us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.730s 170.150us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.780s 113.385us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.450s 46.129us 5 5 100.00
edn_csr_aliasing 1.730s 170.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 93.960s 9128.651us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 93.960s 9128.651us 100 100 100.00
genbits 100 100 100.00
edn_genbits 93.960s 9128.651us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.400s 27.089us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.630s 179.623us 200 200 100.00
errs 100 100 100.00
edn_err 1.710s 22.828us 100 100 100.00
disable 96 100 96.00
edn_disable 1.390s 21.641us 50 50 100.00
edn_disable_auto_req_mode 9.710s 500.000us 46 50 92.00
stress_all 30 30 100.00
edn_stress_all 7.660s 393.558us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.390s 43.279us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.350s 19.725us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.030s 292.958us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.030s 292.958us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.220s 24.718us 1 1 100.00
edn_csr_rw 1.450s 46.129us 5 5 100.00
edn_csr_aliasing 1.730s 170.150us 1 1 100.00
edn_same_csr_outstanding 1.740s 38.215us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.220s 24.718us 1 1 100.00
edn_csr_rw 1.450s 46.129us 5 5 100.00
edn_csr_aliasing 1.730s 170.150us 1 1 100.00
edn_same_csr_outstanding 1.740s 38.215us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 11.030s 3201.236us 5 5 100.00
edn_tl_intg_err 5.250s 355.418us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.510s 33.148us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.630s 179.623us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.030s 3201.236us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.030s 3201.236us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 11.030s 3201.236us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 11.030s 3201.236us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.630s 179.623us 200 200 100.00
edn_sec_cm 11.030s 3201.236us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.630s 179.623us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 5.250s 355.418us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 120.370s 6338.987us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 45396784316106674344817848294681286023034887213482013292574430955441929248175 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 35107779044500129728048374350704999289266746950135885288756941903415440354920 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 34177079831465348341211051730455629308690871294875279931767299775352731861631 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 138582002090033103230774526641887203810053934232397020791025146902396356051 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 75601923613616335846145072728069939828963957592970915216957499403585449926908 179
UVM_INFO @ 2026751733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 26945105943754008366707460648391399259542057270102603821330878262970934302015 122
UVM_INFO @ 1013799079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 31279527006121686272954261817250248371228346549330675444946929505022260408503 275
UVM_INFO @ 1008936218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 82598115793416845106877565348641768247171179024078766760842700349337980907569 164
/nightly/current_run/scratch/reseed_opt/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 821625141 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup