Simulation Results: edn/edn1

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.31 %
  • code
  • 96.35 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.85 %
  • toggle
  • 96.08 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.130s 20.463us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.170s 22.080us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.200s 14.077us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.690s 570.070us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 437.257us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.490s 24.734us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.200s 14.077us 5 5 100.00
edn_csr_aliasing 1.150s 437.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.540s 569.511us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.540s 569.511us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.540s 569.511us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.400s 19.693us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.600s 155.834us 200 200 100.00
errs 100 100 100.00
edn_err 1.530s 53.850us 100 100 100.00
disable 94 100 94.00
edn_disable 1.150s 19.744us 50 50 100.00
edn_disable_auto_req_mode 2.900s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 7.230s 728.571us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.240s 18.324us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.190s 13.968us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.260s 488.239us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.260s 488.239us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.170s 22.080us 1 1 100.00
edn_csr_rw 1.200s 14.077us 5 5 100.00
edn_csr_aliasing 1.150s 437.257us 1 1 100.00
edn_same_csr_outstanding 1.270s 34.410us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.170s 22.080us 1 1 100.00
edn_csr_rw 1.200s 14.077us 5 5 100.00
edn_csr_aliasing 1.150s 437.257us 1 1 100.00
edn_same_csr_outstanding 1.270s 34.410us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.100s 276.757us 5 5 100.00
edn_tl_intg_err 2.770s 333.398us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 0.990s 18.610us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.600s 155.834us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.100s 276.757us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.100s 276.757us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.100s 276.757us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.100s 276.757us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.600s 155.834us 200 200 100.00
edn_sec_cm 4.100s 276.757us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.600s 155.834us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.770s 333.398us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 113.740s 10458.364us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 51831653269039374423814756625901243794755361792998452916566250033476060941098 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69072651830427727383614067261761551871163280637068063652845007617869617126935 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 48773409321520467534575057220047771804311741796745674633979805944421168736355 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 81824615526353670028215199601865033898448801218674707734255899205787441680296 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 9606232216012202379363493425436339604232903845119578820424136901967042842493 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 61328417199897365869101873462301422034418406694799528002780527273670542117171 113
UVM_INFO @ 144248540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 37247067738623753902991552400782392781345783981756209432695235665091243901623 166
UVM_INFO @ 1627111608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 85602775128711873712230415013660316714042634282456707932474522548186515119859 400
UVM_INFO @ 2410076363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 60311425366836324764329045731726454623109424450506185741667250650325809312917 124
UVM_INFO @ 10458364414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 105457684662669104560287924005651517375197451026272721675720758399527956275306 88
UVM_INFO @ 32063902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---