Simulation Results: flash_ctrl

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.06 %
  • code
  • 95.91 %
  • assert
  • 96.84 %
  • func
  • 98.42 %
  • line
  • 96.10 %
  • branch
  • 97.42 %
  • cond
  • 94.87 %
  • toggle
  • 98.66 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
98.50%
V2S
99.16%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 123.530s 153.020us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 21.450s 17.603us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 24.090s 48.883us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 11.340s 22.303us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 48.160s 22115.727us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 28.740s 648.486us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 13.480s 63.229us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 11.340s 22.303us 5 5 100.00
flash_ctrl_csr_aliasing 28.740s 648.486us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.600s 26.626us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.620s 18.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 15.520s 23.930us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 87.710s 355.391us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1412.210s 334112.525us 3 3 100.00
flash_ctrl_hw_rma_reset 696.610s 630443.396us 20 20 100.00
flash_ctrl_lcmgr_intg 13.200s 29.213us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 1945.640s 289703.912us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 263.140s 2706.875us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 178.240s 10584.087us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3287.960s 376619.927us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 99.150s 1436.541us 5 5 100.00
rd_buff_eviction_w_ecc 101 105 96.19
flash_ctrl_rw_evict 31.600s 53.661us 38 40 95.00
flash_ctrl_rw_evict_all_en 29.580s 29.269us 38 40 95.00
flash_ctrl_re_evict 33.790s 106.749us 25 25 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 215.520s 754.767us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 215.520s 754.767us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 858.200s 29101.076us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 26.520s 400.002us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 635.260s 435.616us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 633.070s 8745.374us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 463.930s 3705.732us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1135.460s 1734.917us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 12.310s 37.880us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 164.650s 1487.907us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 18.070s 34.010us 50 50 100.00
flash_ctrl_connect 79 80 98.75
flash_ctrl_connect 59.330s 10001.721us 79 80 98.75
stress_all 5 5 100.00
flash_ctrl_stress_all 1036.950s 466.420us 5 5 100.00
secret_partition 129 130 99.23
flash_ctrl_hw_sec_otp 177.040s 3330.828us 50 50 100.00
flash_ctrl_otp_reset 107.020s 44.513us 79 80 98.75
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1412.210s 334112.525us 3 3 100.00
interrupts 97 100 97.00
flash_ctrl_intr_rd 167.210s 9853.458us 38 40 95.00
flash_ctrl_intr_wr 72.720s 2146.887us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 389.240s 44188.620us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 3604.014s 0.000us 9 10 90.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 68.520s 1915.555us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 54.820s 1656.592us 5 5 100.00
double_bit_err 35 35 100.00
flash_ctrl_read_word_sweep_derr 18.930s 98.943us 5 5 100.00
flash_ctrl_ro_derr 108.310s 3155.934us 10 10 100.00
flash_ctrl_rw_derr 216.520s 8652.048us 10 10 100.00
flash_ctrl_derr_detect 239.560s 4799.985us 5 5 100.00
flash_ctrl_integrity 446.400s 4374.159us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 17.870s 205.097us 5 5 100.00
flash_ctrl_ro_serr 110.520s 757.660us 10 10 100.00
flash_ctrl_rw_serr 222.930s 35102.550us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 68.920s 2234.388us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 61.230s 3978.087us 5 5 100.00
scramble 58 62 93.55
flash_ctrl_wo 3604.012s 0.000us 18 20 90.00
flash_ctrl_write_word_sweep 11.400s 83.740us 1 1 100.00
flash_ctrl_read_word_sweep 11.420s 30.185us 1 1 100.00
flash_ctrl_ro 110.910s 5647.012us 18 20 90.00
flash_ctrl_rw 421.250s 21209.570us 20 20 100.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 33.020s 321.543us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 680.830s 163795.064us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 236.990s 10021.343us 20 20 100.00
alert_test 9 10 90.00
flash_ctrl_alert_test 53.950s 10002.184us 9 10 90.00
intr_test 10 10 100.00
flash_ctrl_intr_test 11.410s 61.421us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
flash_ctrl_tl_errors 17.850s 58.403us 25 25 100.00
tl_d_illegal_access 25 25 100.00
flash_ctrl_tl_errors 17.850s 58.403us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 24.090s 48.883us 1 1 100.00
flash_ctrl_csr_rw 11.340s 22.303us 5 5 100.00
flash_ctrl_csr_aliasing 28.740s 648.486us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.060s 832.287us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 24.090s 48.883us 1 1 100.00
flash_ctrl_csr_rw 11.340s 22.303us 5 5 100.00
flash_ctrl_csr_aliasing 28.740s 648.486us 1 1 100.00
flash_ctrl_same_csr_outstanding 18.060s 832.287us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 49.310s 353.990us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 49.310s 353.990us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 49.310s 353.990us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 49.310s 353.990us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 50.090s 499.839us 20 20 100.00
tl_intg_err 30 30 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
flash_ctrl_tl_intg_err 439.870s 2544.192us 25 25 100.00
sec_cm_reg_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 439.870s 2544.192us 25 25 100.00
sec_cm_host_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 439.870s 2544.192us 25 25 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 26.610s 66.037us 3 3 100.00
flash_ctrl_wr_intg 12.740s 175.329us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 123.530s 153.020us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 258 260 99.23
flash_ctrl_otp_reset 107.020s 44.513us 79 80 98.75
flash_ctrl_disable 18.070s 34.010us 50 50 100.00
flash_ctrl_sec_info_access 73.600s 39192.604us 50 50 100.00
flash_ctrl_connect 59.330s 10001.721us 79 80 98.75
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 11.950s 29.839us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 11.340s 22.303us 5 5 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 49.310s 353.990us 20 20 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 11.340s 22.303us 5 5 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 49.310s 353.990us 20 20 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 11.340s 22.303us 5 5 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 49.310s 353.990us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 18.070s 34.010us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 26.610s 66.037us 3 3 100.00
flash_ctrl_access_after_disable 12.810s 30.338us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 22.470s 27.197us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 18.070s 34.010us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 26.520s 400.002us 10 10 100.00
sec_cm_mem_scramble 20 20 100.00
flash_ctrl_rw 421.250s 21209.570us 20 20 100.00
sec_cm_mem_integrity 25 25 100.00
flash_ctrl_rw_serr 222.930s 35102.550us 10 10 100.00
flash_ctrl_rw_derr 216.520s 8652.048us 10 10 100.00
flash_ctrl_integrity 446.400s 4374.159us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1412.210s 334112.525us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 23.640s 752.599us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 3 5 60.00
flash_ctrl_phy_host_grant_err 11.920s 23.961us 3 5 60.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 11.770s 22.850us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2116.810s 985.047us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 34.460s 57.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 330.140s 711.888us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 3 test runs
flash_ctrl_rw_evict_all_en 7429681221235415272355964298710300524827974371146043212772466087285292241331 113
UVM_INFO @ 18652.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict_all_en 75900725786942005146740125169985877542573606926707397605272263678632999220391 113
UVM_INFO @ 10795.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict 89321305626825248500340642799905818292367905423030306313708551243259247521960 113
UVM_INFO @ 24514.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 2 test runs
flash_ctrl_phy_host_grant_err 87515207779195331230887191292478741690556374566483084622428972371531561257642 125
UVM_ERROR @ 12957.3 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 12957.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 113157831210947212445393044965272536813779468823893644924488428399715544365592 130
UVM_ERROR @ 19782.3 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 19782.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
flash_ctrl_wo 21697335794264607573937428134397048988301671786830839329807428395494914962139 None
flash_ctrl_intr_wr_slow_flash 57108164895101069931320916929784394596055272837440258783598107330801219240280 None
UVM_FATAL (cip_base_vseq.sv:454) [flash_ctrl_common_vseq] wait timeout occurred! 1 test run
flash_ctrl_alert_test 64146688673243211820119437799946101206570846336365798826888012817425425090260 113
UVM_INFO @ 10002183.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * 1 test run
flash_ctrl_rw_evict 26420593744532638883416192758897881087289926439600015569953968134681626948081 113
UVM_INFO @ 26715.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 1 test run
flash_ctrl_ro 59482738957834528529087725021737647210687443059764813890491160032034677695250 113
UVM_INFO @ 356815.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_wo 5965573506342527532277041833164051285760105032085683158570979193886666126683 113
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly 1 test run
flash_ctrl_ro 27349430466518896073057079610135829509235133086326420523575613744146205704733 113
UVM_INFO @ 1931128.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp dd19a47d_efd0cd39:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 5125262465516033034918909465915460438551418338525240319587770422936397442481 113
UVM_INFO @ 938034.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'dst_req_o' 1 test run
flash_ctrl_otp_reset 28989006356234313210047189944159263129234131683741436726058239033501577895235 195
UVM_ERROR @ 29666.1 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq
UVM_INFO @ 29666.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *c00dae1_872da0fb:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 65154740491707073965126625363076929757505650786367632690790849166038025925000 113
UVM_INFO @ 1487157.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [flash_ctrl_connect_vseq] wait timeout occurred! 1 test run
flash_ctrl_connect 62431903190579627452473690399196530119291578569790265839564608315731840288530 113
UVM_INFO @ 10001721.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---