Simulation Results: hmac

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.90 %
  • code
  • 99.33 %
  • assert
  • 97.36 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.91 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.520s 1042.181us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.150s 112.088us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.150s 55.287us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.890s 925.070us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.370s 62.573us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 2.730s 35.026us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.150s 55.287us 5 5 100.00
hmac_csr_aliasing 3.370s 62.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 92.180s 6714.584us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 78.910s 12051.056us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 288.970s 32353.565us 30 30 100.00
hmac_test_sha384_vectors 574.150s 64006.691us 75 75 100.00
hmac_test_sha512_vectors 556.640s 13771.817us 75 75 100.00
hmac_test_hmac256_vectors 15.430s 364.418us 50 50 100.00
hmac_test_hmac384_vectors 16.210s 1413.917us 60 60 100.00
hmac_test_hmac512_vectors 20.160s 407.555us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 40.270s 870.301us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1240.080s 6898.418us 10 10 100.00
error 10 10 100.00
hmac_error 111.960s 67610.305us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 110.350s 18867.454us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.520s 1042.181us 10 10 100.00
hmac_long_msg 92.180s 6714.584us 10 10 100.00
hmac_back_pressure 78.910s 12051.056us 25 25 100.00
hmac_datapath_stress 1240.080s 6898.418us 10 10 100.00
hmac_burst_wr 40.270s 870.301us 50 50 100.00
hmac_stress_all 2841.590s 411137.708us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.520s 1042.181us 10 10 100.00
hmac_long_msg 92.180s 6714.584us 10 10 100.00
hmac_back_pressure 78.910s 12051.056us 25 25 100.00
hmac_datapath_stress 1240.080s 6898.418us 10 10 100.00
hmac_wipe_secret 110.350s 18867.454us 10 10 100.00
hmac_test_sha256_vectors 288.970s 32353.565us 30 30 100.00
hmac_test_sha384_vectors 574.150s 64006.691us 75 75 100.00
hmac_test_sha512_vectors 556.640s 13771.817us 75 75 100.00
hmac_test_hmac256_vectors 15.430s 364.418us 50 50 100.00
hmac_test_hmac384_vectors 16.210s 1413.917us 60 60 100.00
hmac_test_hmac512_vectors 20.160s 407.555us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.520s 1042.181us 10 10 100.00
hmac_long_msg 92.180s 6714.584us 10 10 100.00
hmac_back_pressure 78.910s 12051.056us 25 25 100.00
hmac_datapath_stress 1240.080s 6898.418us 10 10 100.00
hmac_burst_wr 40.270s 870.301us 50 50 100.00
hmac_error 111.960s 67610.305us 10 10 100.00
hmac_wipe_secret 110.350s 18867.454us 10 10 100.00
hmac_test_sha256_vectors 288.970s 32353.565us 30 30 100.00
hmac_test_sha384_vectors 574.150s 64006.691us 75 75 100.00
hmac_test_sha512_vectors 556.640s 13771.817us 75 75 100.00
hmac_test_hmac256_vectors 15.430s 364.418us 50 50 100.00
hmac_test_hmac384_vectors 16.210s 1413.917us 60 60 100.00
hmac_test_hmac512_vectors 20.160s 407.555us 75 75 100.00
hmac_stress_all 2841.590s 411137.708us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2841.590s 411137.708us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.940s 39.722us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.980s 17.181us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.740s 223.819us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.740s 223.819us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.150s 112.088us 1 1 100.00
hmac_csr_rw 1.150s 55.287us 5 5 100.00
hmac_csr_aliasing 3.370s 62.573us 1 1 100.00
hmac_same_csr_outstanding 2.870s 404.698us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.150s 112.088us 1 1 100.00
hmac_csr_rw 1.150s 55.287us 5 5 100.00
hmac_csr_aliasing 3.370s 62.573us 1 1 100.00
hmac_same_csr_outstanding 2.870s 404.698us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.430s 353.728us 5 5 100.00
hmac_tl_intg_err 5.320s 283.820us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.320s 283.820us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.520s 1042.181us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.180s 248.932us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 1199.030s 151730.166us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.660s 95.026us 1 1 100.00