Simulation Results: keymgr

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.78 %
  • code
  • 98.50 %
  • assert
  • 97.72 %
  • func
  • 91.11 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 98.24 %
  • toggle
  • 98.51 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.04%
V2S
98.73%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
keymgr_smoke 7.410s 433.184us 20 20 100.00
random 20 20 100.00
keymgr_random 58.110s 4478.073us 20 20 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.370s 51.666us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.970s 186.008us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 7.410s 643.940us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 4.690s 298.247us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 2.350s 33.797us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.970s 186.008us 5 5 100.00
keymgr_csr_aliasing 4.690s 298.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 85.510s 10276.481us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 11.950s 3397.123us 20 20 100.00
keymgr_sideload_kmac 37.350s 2590.269us 20 20 100.00
keymgr_sideload_aes 33.420s 1700.840us 20 20 100.00
keymgr_sideload_otbn 28.880s 3046.415us 20 20 100.00
direct_to_disabled_state 20 20 100.00
keymgr_direct_to_disabled 14.160s 1342.402us 20 20 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 18.290s 775.403us 48 50 96.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 15.630s 5398.020us 20 20 100.00
invalid_sw_input 19 20 95.00
keymgr_sw_invalid_input 28.130s 12515.882us 19 20 95.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 33.610s 1789.390us 49 50 98.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 5.480s 725.005us 20 20 100.00
stress_all 50 50 100.00
keymgr_stress_all 226.300s 9168.182us 50 50 100.00
intr_test 10 10 100.00
keymgr_intr_test 1.260s 15.107us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.300s 61.624us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 4.670s 434.651us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 4.670s 434.651us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.370s 51.666us 1 1 100.00
keymgr_csr_rw 1.970s 186.008us 5 5 100.00
keymgr_csr_aliasing 4.690s 298.247us 1 1 100.00
keymgr_same_csr_outstanding 2.870s 104.734us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.370s 51.666us 1 1 100.00
keymgr_csr_rw 1.970s 186.008us 5 5 100.00
keymgr_csr_aliasing 4.690s 298.247us 1 1 100.00
keymgr_same_csr_outstanding 2.870s 104.734us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
keymgr_tl_intg_err 8.170s 504.230us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.530s 295.507us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.530s 295.507us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.530s 295.507us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.530s 295.507us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.180s 2735.808us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 8.170s 504.230us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.530s 295.507us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 85.510s 10276.481us 50 50 100.00
sec_cm_reseed_config_regwen 25 25 100.00
keymgr_random 58.110s 4478.073us 20 20 100.00
keymgr_csr_rw 1.970s 186.008us 5 5 100.00
sec_cm_sw_binding_config_regwen 25 25 100.00
keymgr_random 58.110s 4478.073us 20 20 100.00
keymgr_csr_rw 1.970s 186.008us 5 5 100.00
sec_cm_max_key_ver_config_regwen 25 25 100.00
keymgr_random 58.110s 4478.073us 20 20 100.00
keymgr_csr_rw 1.970s 186.008us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 18.290s 775.403us 48 50 96.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 33.610s 1789.390us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 33.610s 1789.390us 49 50 98.00
sec_cm_hw_key_sw_noaccess 20 20 100.00
keymgr_random 58.110s 4478.073us 20 20 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 10.570s 544.282us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_ctrl_fsm_consistency 49 50 98.00
keymgr_custom_cm 13.110s 1318.681us 49 50 98.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 18.290s 775.403us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 49 50 98.00
keymgr_custom_cm 13.110s 1318.681us 49 50 98.00
sec_cm_kmac_if_done_ctrl_consistency 49 50 98.00
keymgr_custom_cm 13.110s 1318.681us 49 50 98.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 49 50 98.00
keymgr_custom_cm 13.110s 1318.681us 49 50 98.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.480s 1062.615us 5 5 100.00
sec_cm_ctrl_key_integrity 49 50 98.00
keymgr_custom_cm 13.110s 1318.681us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 12 20 60.00
keymgr_stress_all_with_rand_reset 20.050s 2922.256us 12 20 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
keymgr_stress_all_with_rand_reset 100304393300741705139688201168301092826266321388376777096332749788582256072135 560
UVM_INFO @ 355775203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 8547407064217809897429188088072756331545535609034453844246961281314355074691 987
UVM_INFO @ 340471012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 108713413484098675910006490171359399166306097911915181697659573288004655860219 107
UVM_INFO @ 223705122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 42853803623659472567758123497235959482518801876312209831674997659692202398091 2043
UVM_INFO @ 2083456283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 109941052513226713230638721321093407387663449764726227799742190437930780012951 874
UVM_INFO @ 1165795832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 111463821564608156295019079881838731604929038972855720761461009629864075665288 740
UVM_INFO @ 248499676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 89910539363256816140644699837409091446525889341739095048940731299990533428596 163
UVM_INFO @ 369496811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 61368530642916038765391013206342835099328223997553073401932348097487984095727 156
UVM_INFO @ 123686466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 3 test runs
keymgr_sw_invalid_input 100937395113685404689875781426326228308357639106828098685280083503386153592730 211
UVM_INFO @ 26299225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 12941757239573582019628740789370128161851031303900555388026480757910555320262 90
UVM_INFO @ 52901859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_custom_cm 29650140406568594764756166428130264437426597829001224419216605301604398116004 215
UVM_INFO @ 33734003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly 1 test run
keymgr_hwsw_invalid_input 112514372986240160298957659102916906246381368437297293204810798903939461062424 342
UVM_INFO @ 46110527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 1 test run
keymgr_lc_disable 82837191816655302259394426093626347560782346326963106878996323792567141779239 98
UVM_INFO @ 53479064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---