Simulation Results: kmac/masked

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 94.25 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 60.850s 13064.927us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.370s 33.087us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.570s 30.643us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 15.830s 4817.974us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.320s 250.750us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 3.510s 629.595us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.570s 30.643us 5 5 100.00
kmac_csr_aliasing 5.320s 250.750us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.910s 21.945us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.270s 59.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 2699.210s 1095453.967us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 1360.310s 74841.525us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1894.940s 72832.918us 5 5 100.00
kmac_test_vectors_sha3_256 1704.860s 285760.614us 5 5 100.00
kmac_test_vectors_sha3_384 1864.550s 135346.026us 5 5 100.00
kmac_test_vectors_sha3_512 959.730s 154819.159us 5 5 100.00
kmac_test_vectors_shake_128 2733.340s 722569.707us 5 5 100.00
kmac_test_vectors_shake_256 1786.530s 76465.821us 5 5 100.00
kmac_test_vectors_kmac 3.560s 185.581us 5 5 100.00
kmac_test_vectors_kmac_xof 3.450s 417.969us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 383.890s 14205.303us 20 20 100.00
app 25 25 100.00
kmac_app 340.410s 45987.051us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 359.500s 68310.234us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 339.590s 98179.559us 20 20 100.00
error 20 20 100.00
kmac_error 468.560s 20363.703us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 13.950s 14803.189us 20 20 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.500s 558.063us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 40.990s 888.294us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 50.760s 2203.022us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 84.350s 27616.053us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 30.520s 706.774us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2739.350s 86630.014us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.200s 13.507us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.260s 40.786us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 3.640s 159.430us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 3.640s 159.430us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.370s 33.087us 1 1 100.00
kmac_csr_rw 1.570s 30.643us 5 5 100.00
kmac_csr_aliasing 5.320s 250.750us 1 1 100.00
kmac_same_csr_outstanding 3.060s 348.617us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.370s 33.087us 1 1 100.00
kmac_csr_rw 1.570s 30.643us 5 5 100.00
kmac_csr_aliasing 5.320s 250.750us 1 1 100.00
kmac_same_csr_outstanding 3.060s 348.617us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.650s 712.618us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.650s 712.618us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.650s 712.618us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.650s 712.618us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.120s 225.776us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 97.570s 63724.441us 5 5 100.00
kmac_tl_intg_err 5.720s 250.718us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 5.720s 250.718us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 30.520s 706.774us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 60.850s 13064.927us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 383.890s 14205.303us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.650s 712.618us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 97.570s 63724.441us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 97.570s 63724.441us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 97.570s 63724.441us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 60.850s 13064.927us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 30.520s 706.774us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 97.570s 63724.441us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 331.040s 41598.101us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 60.850s 13064.927us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 364.030s 91585.170us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 2 test runs
kmac_stress_all_with_rand_reset 36926146802089657133954708752618542363224456657072266891469704675714523936014 345
UVM_INFO @ 6833410556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 70940606779546534439680950875561911209289229092398790411548905043569398255291 333
UVM_INFO @ 2610554281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---