Simulation Results: kmac/unmasked

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.45 %
  • code
  • 92.21 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
95.97%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 56.710s 2783.153us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.310s 23.566us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.510s 50.942us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 14.910s 9639.439us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.750s 76.183us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.940s 81.506us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.510s 50.942us 5 5 100.00
kmac_csr_aliasing 4.750s 76.183us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.110s 13.408us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.790s 19.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 3976.980s 98612.884us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 817.780s 65112.272us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2388.560s 184550.133us 5 5 100.00
kmac_test_vectors_sha3_256 2213.490s 358467.525us 5 5 100.00
kmac_test_vectors_sha3_384 1319.450s 44199.382us 5 5 100.00
kmac_test_vectors_sha3_512 864.010s 45592.554us 5 5 100.00
kmac_test_vectors_shake_128 1624.180s 42102.890us 5 5 100.00
kmac_test_vectors_shake_256 1700.810s 59586.661us 5 5 100.00
kmac_test_vectors_kmac 2.890s 99.904us 5 5 100.00
kmac_test_vectors_kmac_xof 2.470s 83.549us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 379.960s 59526.447us 20 20 100.00
app 25 25 100.00
kmac_app 291.370s 18143.799us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 258.740s 31201.224us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 259.900s 44194.426us 20 20 100.00
error 20 20 100.00
kmac_error 316.550s 90489.948us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 10.240s 5738.048us 20 20 100.00
sideload_invalid 33 50 66.00
kmac_sideload_invalid 166.610s 10037.377us 33 50 66.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 32.540s 5025.420us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.280s 8300.611us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 67.440s 32332.040us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 52.210s 5422.684us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2615.210s 90070.450us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.200s 24.530us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.150s 20.057us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.550s 167.563us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.550s 167.563us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.310s 23.566us 1 1 100.00
kmac_csr_rw 1.510s 50.942us 5 5 100.00
kmac_csr_aliasing 4.750s 76.183us 1 1 100.00
kmac_same_csr_outstanding 2.100s 61.221us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.310s 23.566us 1 1 100.00
kmac_csr_rw 1.510s 50.942us 5 5 100.00
kmac_csr_aliasing 4.750s 76.183us 1 1 100.00
kmac_same_csr_outstanding 2.100s 61.221us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.520s 511.419us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.520s 511.419us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.520s 511.419us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.520s 511.419us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.660s 957.396us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 63.170s 17782.549us 5 5 100.00
kmac_tl_intg_err 5.580s 238.282us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 5.580s 238.282us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 52.210s 5422.684us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 56.710s 2783.153us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 379.960s 59526.447us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.520s 511.419us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 63.170s 17782.549us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 63.170s 17782.549us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 63.170s 17782.549us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 56.710s 2783.153us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 52.210s 5422.684us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 63.170s 17782.549us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 249.450s 12121.452us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 56.710s 2783.153us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 325.370s 19396.317us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 3 test runs
kmac_sideload_invalid 111987975576291563178692882732739296600891444273115382319272152971327133958075 78
UVM_INFO @ 10024744346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 97866648709933158944091255595316324875504950504376418178819246133449928529700 78
UVM_INFO @ 10032461741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 14506143488521126215152267399393234480316810556701469147224888549274252378115 78
UVM_INFO @ 10033627301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 3 test runs
kmac_sideload_invalid 37048471335513719316917552933983439967108915796377562867048414400118912848693 82
UVM_INFO @ 10237262626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 22590462654371435282581475807547207454992451273146616415339640464898068525572 82
UVM_INFO @ 10159481796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 91739808945951612285669115362278422678033885347777703346884411918534503216838 83
UVM_INFO @ 10238217901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 2 test runs
kmac_sideload_invalid 11655799428213305862475987193714219466327285136114204706023708247914651066181 79
UVM_INFO @ 10020744387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 107877397530858311287347523356870867120424541498510642935845064645584556052160 79
UVM_INFO @ 10038799708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) 2 test runs
kmac_sideload_invalid 103090982465264956979645167386811529433214020356958046373022452115126831888424 85
UVM_INFO @ 10044021854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 101712594191357757955679743561387547038191120167981260361474574053486935000307 85
UVM_INFO @ 10037376856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 2 test runs
kmac_sideload_invalid 1602050285628842123299063039872201445035963605032151226367948420384203854410 90
UVM_INFO @ 10167836594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 26010361155268763153114064950707782285547313985152164726757733705577275135576 89
UVM_INFO @ 10420406283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 19996164403167595472291329147216514687345994803403674332285604990487499366357 427
UVM_INFO @ 26932991932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
kmac_sideload_invalid 13237496850598679965120158089597816694966179959096339548737432421317295892843 86
UVM_INFO @ 10622112471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 70401529594089024025098752472793107016839209903074878844605877376712034987320 153
UVM_INFO @ 3879945270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
kmac_sideload_invalid 57378055878564492730394066075915323817510868884665729705226082960780905090116 81
UVM_INFO @ 10036691285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) 1 test run
kmac_sideload_invalid 27677500629056597335940208064813493576129163557021293575606804492355978245534 87
UVM_INFO @ 10321551500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) 1 test run
kmac_sideload_invalid 24478264153998644264571703231808591091112970775470345912717471242477169767154 96
UVM_INFO @ 10483865714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) 1 test run
kmac_sideload_invalid 9812764166212389142432942281080190245008461067291358974150845489265331800215 103
UVM_INFO @ 10217557139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---