Simulation Results: lc_ctrl/volatile_unlock_disabled

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.14 %
  • code
  • 86.02 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.28 %
  • branch
  • 94.14 %
  • cond
  • 81.84 %
  • toggle
  • 89.54 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
99.20%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
lc_ctrl_smoke 5.740s 778.137us 10 10 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.390s 15.613us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.360s 51.767us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.090s 129.768us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.490s 18.217us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.790s 53.272us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.360s 51.767us 5 5 100.00
lc_ctrl_csr_aliasing 1.490s 18.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 10 10 100.00
lc_ctrl_state_post_trans 7.260s 237.154us 10 10 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.690s 499.053us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.330s 13.711us 10 10 100.00
lc_prog_failure 10 10 100.00
lc_ctrl_prog_failure 3.580s 141.648us 10 10 100.00
lc_state_failure 10 10 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_errors 9 10 90.00
lc_ctrl_errors 12.960s 790.688us 9 10 90.00
security_escalation 98 100 98.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_prog_failure 3.580s 141.648us 10 10 100.00
lc_ctrl_errors 12.960s 790.688us 9 10 90.00
lc_ctrl_security_escalation 13.760s 476.824us 10 10 100.00
lc_ctrl_jtag_state_failure 88.700s 4428.037us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.370s 3358.565us 20 20 100.00
lc_ctrl_jtag_errors 60.860s 12004.609us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 7.950s 1766.961us 20 20 100.00
lc_ctrl_jtag_state_post_trans 28.640s 1066.004us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.370s 3358.565us 20 20 100.00
lc_ctrl_jtag_errors 60.860s 12004.609us 19 20 95.00
lc_ctrl_jtag_access 24.380s 1011.302us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.510s 4864.310us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.420s 287.273us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.150s 136.560us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 33.280s 3874.652us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 23.700s 2138.798us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.260s 52.263us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.960s 356.928us 10 10 100.00
lc_ctrl_jtag_alert_test 3.750s 597.376us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 14.170s 5918.056us 10 10 100.00
lc_ctrl_volatile_unlock 9 10 90.00
lc_ctrl_volatile_unlock_smoke 1.480s 15.266us 9 10 90.00
stress_all 10 10 100.00
lc_ctrl_stress_all 215.410s 14455.176us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.510s 68.919us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.310s 91.200us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.310s 91.200us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.390s 15.613us 1 1 100.00
lc_ctrl_csr_rw 1.360s 51.767us 5 5 100.00
lc_ctrl_csr_aliasing 1.490s 18.217us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.530s 52.196us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.390s 15.613us 1 1 100.00
lc_ctrl_csr_rw 1.360s 51.767us 5 5 100.00
lc_ctrl_csr_aliasing 1.490s 18.217us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.530s 52.196us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
lc_ctrl_tl_intg_err 4.010s 116.699us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.010s 116.699us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.690s 499.053us 10 10 100.00
sec_cm_manuf_state_sparse 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_transition_ctr_sparse 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_state_config_sparse 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_main_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_kmac_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_main_fsm_local_esc 15 15 100.00
lc_ctrl_state_failure 13.660s 682.328us 10 10 100.00
lc_ctrl_sec_cm 10.240s 629.916us 5 5 100.00
sec_cm_main_fsm_global_esc 10 10 100.00
lc_ctrl_security_escalation 13.760s 476.824us 10 10 100.00
sec_cm_main_ctrl_flow_consistency 30 30 100.00
lc_ctrl_state_post_trans 7.260s 237.154us 10 10 100.00
lc_ctrl_jtag_state_post_trans 28.640s 1066.004us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.790s 1772.563us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.790s 1772.563us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 13.550s 2898.832us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.780s 2645.275us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.780s 2645.275us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 74.530s 3043.950us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 68955944613425139454058910306695909683899209414633344081333540078201221155724 2710
UVM_INFO @ 7127421516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64144612971022034442699708114651351344004801722326031739921344337285850165046 151
UVM_INFO @ 520823293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 36337665943775717846578813193425287276648766668315045898957764896602101144440 3754
UVM_INFO @ 11506848443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63709802048308396593365385929237971489331127798354247164886940385440678536485 150
UVM_INFO @ 108277074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_stress_all_with_rand_reset 27916469441414326329606982398223572124788935253351841635550011108851689636620 4312
UVM_INFO @ 1367863343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 88656691060733407156839186719703281157281742926390793677470171705994596691372 1636
UVM_INFO @ 311101701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 110357996074731320936250117462594763728751188245230523181394370740808758610445 515
UVM_INFO @ 211959043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 40240379633296373280849101783923907879748079524282337008890382737220740528119 3832
UVM_INFO @ 1462166590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout lc_ctrl_regs_reg_block.status.token_error (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
lc_ctrl_volatile_unlock_smoke 21867126789494452437650731006578793022523217435831555143583214163842802517357 148
UVM_INFO @ 120307204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---