Simulation Results: lc_ctrl/volatile_unlock_enabled

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.26 %
  • code
  • 86.38 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.09 %
  • cond
  • 81.83 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
98.94%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
lc_ctrl_smoke 5.510s 467.330us 10 10 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.360s 52.342us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.260s 13.920us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.630s 21.492us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.650s 124.942us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.570s 60.339us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.260s 13.920us 5 5 100.00
lc_ctrl_csr_aliasing 1.650s 124.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 10 10 100.00
lc_ctrl_state_post_trans 9.100s 153.725us 10 10 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.250s 1131.639us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.400s 12.871us 10 10 100.00
lc_prog_failure 10 10 100.00
lc_ctrl_prog_failure 4.070s 172.427us 10 10 100.00
lc_state_failure 10 10 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_errors 10 10 100.00
lc_ctrl_errors 10.050s 279.834us 10 10 100.00
security_escalation 98 100 98.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_prog_failure 4.070s 172.427us 10 10 100.00
lc_ctrl_errors 10.050s 279.834us 10 10 100.00
lc_ctrl_security_escalation 8.700s 337.354us 10 10 100.00
lc_ctrl_jtag_state_failure 77.530s 24899.718us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.770s 2572.930us 20 20 100.00
lc_ctrl_jtag_errors 67.490s 17010.934us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 12.920s 1290.674us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.530s 838.304us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.770s 2572.930us 20 20 100.00
lc_ctrl_jtag_errors 67.490s 17010.934us 18 20 90.00
lc_ctrl_jtag_access 29.730s 7730.356us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 30.900s 5423.851us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.980s 245.839us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.750s 242.838us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 24.160s 5812.984us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 20.050s 4519.837us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.150s 41.733us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.560s 212.075us 10 10 100.00
lc_ctrl_jtag_alert_test 2.830s 419.593us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 36.040s 10408.307us 9 10 90.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.510s 17.062us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 143.230s 40643.498us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.550s 74.899us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.750s 143.539us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.750s 143.539us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.360s 52.342us 1 1 100.00
lc_ctrl_csr_rw 1.260s 13.920us 5 5 100.00
lc_ctrl_csr_aliasing 1.650s 124.942us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.570s 190.735us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.360s 52.342us 1 1 100.00
lc_ctrl_csr_rw 1.260s 13.920us 5 5 100.00
lc_ctrl_csr_aliasing 1.650s 124.942us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.570s 190.735us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
lc_ctrl_tl_intg_err 3.830s 423.868us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.830s 423.868us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.250s 1131.639us 10 10 100.00
sec_cm_manuf_state_sparse 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_transition_ctr_sparse 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_state_config_sparse 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_main_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_kmac_fsm_sparse 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_main_fsm_local_esc 15 15 100.00
lc_ctrl_state_failure 12.200s 5318.882us 10 10 100.00
lc_ctrl_sec_cm 9.410s 244.840us 5 5 100.00
sec_cm_main_fsm_global_esc 10 10 100.00
lc_ctrl_security_escalation 8.700s 337.354us 10 10 100.00
sec_cm_main_ctrl_flow_consistency 30 30 100.00
lc_ctrl_state_post_trans 9.100s 153.725us 10 10 100.00
lc_ctrl_jtag_state_post_trans 18.530s 838.304us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.920s 852.783us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.920s 852.783us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.580s 1921.323us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.680s 2056.269us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.680s 2056.269us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 74.160s 5853.748us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 4617303146354661911719218570230992710304477367593220295751256246390574870481 5061
UVM_INFO @ 4242968837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81763469651021846410858599961581746812858206457147754247936364745246182903940 11296
UVM_INFO @ 2504983073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 21237011861452366240831829860553787707475516240430631232275207523740774983354 4261
UVM_INFO @ 3542168990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26897678578782693559691128281660324681616163288628769171131908088447885637482 1887
UVM_INFO @ 4662564763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_stress_all 88122170919224634816190349745048324016582462128678280850498298736781758316458 7197
UVM_INFO @ 2029103340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 86405174764887582276642906908016662016498173473291634508515202794076395269960 1250
UVM_INFO @ 2550637702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 9291366763138919991440471720945942051558249051239552840264974783106692562195 471
UVM_INFO @ 519975307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! 1 test run
lc_ctrl_jtag_priority 106705005970530117398317821322284154373333711593902672737293729150933959020210 148
UVM_INFO @ 10007308500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---