Simulation Results: otp_ctrl

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.99 %
  • code
  • 86.13 %
  • assert
  • 94.75 %
  • func
  • 92.08 %
  • line
  • 90.35 %
  • branch
  • 86.75 %
  • cond
  • 94.02 %
  • toggle
  • 95.99 %
  • FSM
  • 63.54 %
Validation stages
V1
100.00%
V2
95.39%
V2S
95.15%
V3
18.81%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.810s 203.768us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 29.980s 4348.782us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.200s 1056.876us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.090s 610.121us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.990s 82.491us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.650s 124.738us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 5.040s 1588.443us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.090s 610.121us 5 5 100.00
otp_ctrl_csr_aliasing 2.650s 124.738us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.300s 139.151us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.470s 39.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.210s 642.138us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 8.080s 2194.471us 300 300 100.00
partition_check 36 60 60.00
otp_ctrl_background_chks 27.110s 6184.348us 10 10 100.00
otp_ctrl_check_fail 70.630s 11106.592us 26 50 52.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 13.050s 5032.345us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 42.350s 25170.947us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 36.460s 16657.074us 10 10 100.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 21.160s 2412.253us 10 10 100.00
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
otp_dai_errors 8 10 80.00
otp_ctrl_dai_errs 36.650s 21347.652us 8 10 80.00
otp_macro_errors 4 10 40.00
otp_ctrl_macro_errs 36.870s 4481.649us 4 10 40.00
test_access 10 10 100.00
otp_ctrl_test_access 26.550s 1988.174us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 226.790s 20519.202us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.010s 43.497us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.880s 721.448us 10 10 100.00
tl_d_oob_addr_access 24 25 96.00
otp_ctrl_tl_errors 32.260s 10003.356us 24 25 96.00
tl_d_illegal_access 24 25 96.00
otp_ctrl_tl_errors 32.260s 10003.356us 24 25 96.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.200s 1056.876us 1 1 100.00
otp_ctrl_csr_rw 2.090s 610.121us 5 5 100.00
otp_ctrl_csr_aliasing 2.650s 124.738us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.130s 1776.774us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.200s 1056.876us 1 1 100.00
otp_ctrl_csr_rw 2.090s 610.121us 5 5 100.00
otp_ctrl_csr_aliasing 2.650s 124.738us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.130s 1776.774us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
tl_intg_err 29 30 96.67
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
otp_ctrl_tl_intg_err 84.950s 12908.701us 24 25 96.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_bus_integrity 24 25 96.00
otp_ctrl_tl_intg_err 84.950s 12908.701us 24 25 96.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 29.980s 4348.782us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 29.980s 4348.782us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
sec_cm_part_fsm_local_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
otp_ctrl_macro_errs 36.870s 4481.649us 4 10 40.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
sec_cm_part_fsm_global_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
otp_ctrl_macro_errs 36.870s 4481.649us 4 10 40.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 35.660s 15004.361us 199 200 99.50
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 8.080s 2194.471us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 26 50 52.00
otp_ctrl_check_fail 70.630s 11106.592us 26 50 52.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 42.350s 25170.947us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 42.350s 25170.947us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 42.350s 25170.947us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 42.350s 25170.947us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 42.350s 25170.947us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 29.980s 4348.782us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 42.350s 25170.947us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 29.980s 4348.782us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 215.370s 166042.501us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 13.050s 5032.345us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 29.980s 4348.782us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 29.980s 4348.782us 10 10 100.00
sec_cm_macro_mem_integrity 4 10 40.00
otp_ctrl_macro_errs 36.870s 4481.649us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.530s 3457.364us 1 1 100.00
stress_all_with_rand_reset 18 100 18.00
otp_ctrl_stress_all_with_rand_reset 3600.120s 0.000us 18 100 18.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 48 test runs
otp_ctrl_macro_errs 108614564632354106444101457830494450929926027569559979401665421220715688587125 1606
UVM_INFO @ 441350017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28077122318020453419393536234598619029154777539549593262235662779102994420097 267
UVM_INFO @ 1422063216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 88814510327902357894559707779456790894690250880797113707720436815629683039425 3858
UVM_INFO @ 516828664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 7808113820945428112535732956097173775992490831771173947344263537390044139802 1615
UVM_INFO @ 587743301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107162773545554410031729818390074126884580226103339385521117962432505627090397 12395
UVM_INFO @ 10932852292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 62764408191032389098295874615634840716025105492533763429448987993833032745534 11257
UVM_INFO @ 1325414213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 81445666293143832824947117850966479649932247406431336417545879697550516146622 14385
UVM_INFO @ 19248853356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 15504367812676887216072158363720872000543164702080240326456337103279792863852 1103
UVM_INFO @ 119872369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 51102398072107781843844984369721540817872050370191704109181478193806661958 111
UVM_INFO @ 177858001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95046900833526590972314731827340887758895504532357680774854324519713057055115 5114
UVM_INFO @ 373487253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 41163585686816912659118801192927587864494381866716165524897737993027037469003 1194
UVM_INFO @ 141106458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 58391454946472301537761520048588130161759356629193464618376268200994366171972 4681
UVM_INFO @ 572140295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 96045217516555474152952582294627073250753886802252392559628227409701640721393 9527
UVM_INFO @ 600127324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 28808620314716722849106855396492655380280515346626710983028508277159414786945 4872
UVM_INFO @ 181458080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 110635145359883004728742322033654123347283317324352045932334957829243991576687 339
UVM_INFO @ 180288478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 27612136766001489471580971269575011606344006615258275613773344247389234913517 3450
UVM_INFO @ 1889212649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 30738420789564641662761366262123995127681932751145684231501544922753280146280 10570
UVM_INFO @ 12096913583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49315367555856859762200731212485444472623717238697163493212208870460788886272 43037
UVM_INFO @ 2950667226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 94730881838310121477260944455947459028662946232006346082340648359193579372714 2244
UVM_INFO @ 289977925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40822770763479666827646544829583859560842871784076395539625483382006919063725 965
UVM_INFO @ 109105513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 2181608285511633207116701272506452334189537814369184941829038704332643462818 4235
UVM_INFO @ 692224456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 13642031247404131754664290512615469211413734341163310494859909589255455469135 9746
UVM_INFO @ 1309154146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 52508186717580989703251976343746187583857588073722853694549030029168219673218 8035
UVM_INFO @ 768517806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94783735289606855937924894975971127358190205156072092070300833428423219634012 9062
UVM_INFO @ 41096297298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54088516586625461774731170121609341053427634375079742660775050605097917289158 9473
UVM_INFO @ 640843445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 51142194006522840572558794815900165281234581918563427656160500173442679506514 9947
UVM_INFO @ 15065072723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 32896655860541138067749666857704201095570514861499938357464936896727710809996 9352
UVM_INFO @ 2015791487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73314545154208243426016574942187000446794095477433840047277104545019099037091 927
UVM_INFO @ 156908428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 70174690696352104883871665501150126682729949776960754738163720059021344045725 9561
UVM_INFO @ 592499650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33924825691201572868914866806452266868034425768733672952784331054337839959891 2102
UVM_INFO @ 1032247624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72342738129051692378212154622355813842095271490775859992067190959595778264698 9385
UVM_INFO @ 401144136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69117852171893234295882749401981155322317942836940273596924298638309450941511 21346
UVM_INFO @ 16737171266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78081006670628234296585672726952320703470091029721722501764495566945906991972 1693
UVM_INFO @ 191523364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50606661182788107405476789932187296458321922245915726108909852130322896313882 8686
UVM_INFO @ 34532400691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2277002114411735255333019616071601968892317819916878439828210666884139670772 729
UVM_INFO @ 456616949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 85029592131944953177569303860992121948447743389419163896865609853677195729346 3561
UVM_INFO @ 566568452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 112156763327830115412853486462909722753989264273490934877015177798769649625772 8014
UVM_INFO @ 14753505951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80728972361459456665863130572389949463459913232639624971849573661415859382954 2654
UVM_INFO @ 2203603397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 87176127617939401439998194453836125409722668867678653351831118157100765865992 7444
UVM_INFO @ 1032306968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42770175601125258713177346519576406854098817337287045169210133795156733285101 308
UVM_INFO @ 228183749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 69597109522741679061939385531507529494491468808758662177381607774383282608663 1901
UVM_INFO @ 297625146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42356645217580991976265561685464161665728004198807500726124225272001255750934 4383
UVM_INFO @ 192707809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108461986143316236151796822629836408624658775186902494552202428541938253455629 6038
UVM_INFO @ 11685278026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 33128198178748708846446080056939791468679603185018287740054079032758683499354 839
UVM_INFO @ 219877820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26958828731901542226702785093533264162669895586817047215722025427616588673252 8137
UVM_INFO @ 4830114993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88302867086746540344007765803602141155203266396479754289996475570295985880230 1809
UVM_INFO @ 3117757651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23495267488442196046514640103627972729272656345492630094096180294326681577506 3273
UVM_INFO @ 1509323441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104041833760077635772774272258330699891886787201145758309603044167362829619455 179
UVM_INFO @ 73390174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 39 test runs
otp_ctrl_stress_all_with_rand_reset 51742582363496401026574426414607454602883773104827382715535202864522524728932 26275
UVM_INFO @ 4653184950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14385327538964924788468472889768221027493529335242134625414355690569266438442 92
UVM_INFO @ 26354354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48610771563065264892359042540151752724301281278499615373716009189226545606662 37334
UVM_INFO @ 1665184570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103583019969824668414279195439926396084985704314252349625060591607304245740095 92
UVM_INFO @ 53564116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27714918302091905556578320278215541683408100254145479433173432455843542058838 10674
UVM_INFO @ 16346518691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27367697485338189398806470276056884076458810686137222276872838382730368587742 188
UVM_INFO @ 6393292911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26623852136576687364740329314844878654525420352149885424019063938450349997059 3348
UVM_INFO @ 9285626027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96822800473099393648989185358580165139611697956302907770196285414280674329232 19140
UVM_INFO @ 1174121313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114964453540330460134121568505007917539608101615353125921064782631847487397789 5208
UVM_INFO @ 10842823599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13102978839679724108024522630763212764723833570763580461372976656398509242642 241
UVM_INFO @ 5824981184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66748612928043123653999349324306959683490033784477067587037680287966826031085 29820
UVM_INFO @ 8551648184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5115114380272998542995443325268742621368646120801094414349262131360654369802 6289
UVM_INFO @ 358679357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76337364136469473217091776356349850950169731752913585281839604131135663937129 7928
UVM_INFO @ 1517352464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83786100982564295420500938131046262404773378556755625989513674472837348323227 6232
UVM_INFO @ 1851580880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50346717810773429469550533655409683628318766857367421643582093182272424243573 197
UVM_INFO @ 4987814422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98810880693225469257372950005406975846100993726301616523383285382738719875280 8207
UVM_INFO @ 3274104267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94539474216968761916955421187446123800765521016435859601284921111766308798956 4844
UVM_INFO @ 622321486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44046807136997889897065393887763406125114576616880995829635247507335528680153 92
UVM_INFO @ 34169639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80368826629193805556352622456049392636918463111938396357869117149140683545964 3705
UVM_INFO @ 944925607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79394380119464716627301590777643279423330628390654243588513190682677599773481 5775
UVM_INFO @ 1356043519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82506710162448394709925183261249195491596615663161869515655299149964010458094 7447
UVM_INFO @ 3110297269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36369904456142626327821605995024785631047267735625793697473979482866884062927 5180
UVM_INFO @ 181944106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1692801914627358302145408814654292990778512461312862482176494815367267979679 92
UVM_INFO @ 26065786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79745595014995022407394032849940376184303995790004541942476128007383345932963 92
UVM_INFO @ 54515495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31437224646575559584608634864269982007292945447079103487983329595316868379967 92
UVM_INFO @ 26582160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109904888450062476148822646056728305226126565312643183570673018658108391206967 1530
UVM_INFO @ 86398947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49982689469538706663256053746359796146390125568135149018365591411496022209810 7366
UVM_INFO @ 1483536671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40541561420538199344430698962548681996784282333085192246641682973615766445834 406
UVM_INFO @ 66586017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53963251336565244385085620780139786705497011741198117679817725905048668464045 149
UVM_INFO @ 122357873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24230717164593705816499414238607250301574750671801646429856961888631827779477 23711
UVM_INFO @ 17425870635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30091263440108588313219782064180733187241271903287423892694894542045237753311 92
UVM_INFO @ 432992317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11752372082010084181878486876077804026319759120644714383275552582673775429694 510
UVM_INFO @ 1251502749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114281227875953819512990980590870467806398477780748587341202455362469919910714 92
UVM_INFO @ 431436101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72397812203005585522924314437074554583113169720359439953875064370055166553322 225
UVM_INFO @ 677129037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111219102617210312006123129518056761614215241968667334879911322681774197977908 92
UVM_INFO @ 106597703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95538993129601044052534457098588754830531470239666095167477944224139036255201 37867
UVM_INFO @ 50133341230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9872927865551882180359629249860237921614480024434149412936654646857440252988 21132
UVM_INFO @ 22331265264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56036672611004878109668509633545534158501562390118779615256275702863615829284 2778
UVM_INFO @ 138194111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57141221929228685254442448744765932771599588590685557315406073965556076963724 20984
UVM_INFO @ 16792797298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 13 test runs
otp_ctrl_stress_all_with_rand_reset 98600181395055177982779913562591577306143675523626825121935306755506403458579 191
UVM_INFO @ 3382542590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67746334226157469629447986533798745952328036868049648821000861656009793173613 7525
UVM_INFO @ 6191877268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88573311653878066745245758055180318905144237987524570590867366371157705081413 149
UVM_INFO @ 552177493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74153862145409492992796233168612875452374060712585311937895524803752995968288 4048
UVM_INFO @ 7172972182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112380820091434291264317725219647645119509217306823906131564435229881861327808 5730
UVM_INFO @ 1620758584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58968244783543863510120409647589713787787443993600256930638176058285746841985 17558
UVM_INFO @ 3516736708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 482942022784007114818825933660769054467174083698784333509507705986583835273 10767
UVM_INFO @ 3204514015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28804869045225009233408465880070686759319612088316574366846195993093647440410 9407
UVM_INFO @ 1979301493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5382940467955169995700913825560685399215460716937334886435759107324597534535 16874
UVM_INFO @ 1586377063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114721758287136366256041267466531981719832038969395980011038138872266822180449 2610
UVM_INFO @ 1534413671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96550446869960078946012808031229136003182046646346241524634594461339848327931 1762
UVM_INFO @ 160015112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50656804407020643319147355668911063563929933857237771601997191205260886061890 14685
UVM_INFO @ 22405727663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77950440238679152305065201599330005868654731395550368164980889997109147389273 7291
UVM_INFO @ 1433926016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 5 test runs
otp_ctrl_stress_all_with_rand_reset 59829185749843913113642050382091453871124587240171387897373752865124611865724 48701
UVM_INFO @ 82140999845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96557986452152012058004328322576957934044053745635753265636293442970023228894 10100
UVM_INFO @ 5294894517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11042326918863432513674913018929423022937986947856071853338577087306566606821 92
UVM_INFO @ 54250870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29850854610673992751667321133433477938702133983361159943488362098918494293275 356
UVM_INFO @ 166551510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36667342332675289964337329823213822453350938011976234831974865617846657747258 92
UVM_INFO @ 107865097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [otp_ctrl_common_vseq] wait timeout occurred! 2 test runs
otp_ctrl_tl_errors 79293328598496184249548263840358788680087332965440216123223434498145985471997 89
UVM_INFO @ 10003356465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_tl_intg_err 34486643374011079359947242011602220230108971676022133000694708097219077806357 284
UVM_INFO @ 12908701151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
otp_ctrl_stress_all_with_rand_reset 82037635169715057200084905505100454457085974839630497960845284331377964792278 None
otp_ctrl_stress_all_with_rand_reset 43939799224857829795934319500387669861453202160125411136723909401400505847330 None
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 2 test runs
otp_ctrl_stress_all_with_rand_reset 32073560106000039742545357633381759297756588724986839909743983186350031584864 106
UVM_INFO @ 587108031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72798202963841244855071911581050770798377396057148089208552188938578369907011 11415
UVM_INFO @ 2620071174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_stress_all_with_rand_reset 93143809273649557164359156702649883763303119498792188581735380058658869882380 4735
UVM_INFO @ 7091480985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=128) 1 test run
otp_ctrl_stress_all_with_rand_reset 104712620630078134466400472882529048923007216486113360606969953030016687277878 23549
UVM_INFO @ 26807172541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 11980106812571726537734681889776306701889344417424049064044816689529171108391 20384
UVM_INFO @ 16410287586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 30524727030532001766909415973821525849922076159113463157962975180411576363927 21046
UVM_INFO @ 14896357442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 22950455316981799121987203930683976924104100013533605322942117835350784903405 19466
UVM_INFO @ 2331922121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* 1 test run
otp_ctrl_parallel_lc_esc 37062024068608263172054344008275653526952798731391833776182602974233214269149 2702
UVM_INFO @ 134168772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---