Simulation Results: pwm

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.61 %
  • assert
  • 98.00 %
  • func
  • 98.68 %
  • block
  • 99.56 %
  • line
  • 99.66 %
  • branch
  • 99.29 %
  • toggle
  • 90.87 %
Validation stages
V1
100.00%
V2
99.25%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwm_smoke 5.000s 516.096us 10 10 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 2.000s 20.181us 1 1 100.00
csr_rw 5 5 100.00
pwm_csr_rw 2.000s 49.826us 5 5 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 4.000s 723.687us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 3.000s 165.854us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwm_csr_mem_rw_with_rand_reset 2.000s 30.109us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwm_csr_rw 2.000s 49.826us 5 5 100.00
pwm_csr_aliasing 3.000s 165.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
pulse 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
blink 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
heartbeat 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
resolution 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
multi_channel 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
polarity 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
phase 50 50 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
pwm_phase 73.000s 10506.052us 25 25 100.00
lowpower 25 25 100.00
pwm_rand_output 70.000s 10503.938us 25 25 100.00
perf 10 10 100.00
pwm_perf 68.000s 10503.212us 10 10 100.00
regwen 0 1 0.00
pwm_regwen 192.000s 11044.062us 0 1 0.00
stress_all 25 25 100.00
pwm_stress_all 253.000s 44271.703us 25 25 100.00
alert_test 10 10 100.00
pwm_alert_test 2.000s 15.950us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwm_tl_errors 4.000s 128.571us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwm_tl_errors 4.000s 128.571us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwm_csr_hw_reset 2.000s 20.181us 1 1 100.00
pwm_csr_rw 2.000s 49.826us 5 5 100.00
pwm_csr_aliasing 3.000s 165.854us 1 1 100.00
pwm_same_csr_outstanding 2.000s 62.703us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwm_csr_hw_reset 2.000s 20.181us 1 1 100.00
pwm_csr_rw 2.000s 49.826us 5 5 100.00
pwm_csr_aliasing 3.000s 165.854us 1 1 100.00
pwm_same_csr_outstanding 2.000s 62.703us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwm_tl_intg_err 4.000s 136.183us 25 25 100.00
pwm_sec_cm 2.000s 110.614us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwm_tl_intg_err 4.000s 136.183us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 10 10 100.00
pwm_heartbeat_wrap 54.000s 10944.143us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (pwm_scoreboard.sv:386) scoreboard [scoreboard] 1 test run
pwm_regwen 50786913091063923763303426063884126019948369774955654438655702593489720253631 97
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 11044061904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---