Simulation Results: pwrmgr

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.19 %
  • code
  • 94.69 %
  • assert
  • 96.34 %
  • func
  • 97.53 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.91 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
94.89%
V2S
71.43%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 1.020s 26.595us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 1.020s 53.987us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 1.010s 46.483us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.110s 85.840us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.230s 50.096us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.250s 46.142us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 1.010s 46.483us 5 5 100.00
pwrmgr_csr_aliasing 1.230s 50.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.260s 222.912us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.260s 222.912us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.340s 50.238us 10 10 100.00
pwrmgr_lowpower_invalid 1.030s 55.398us 10 10 100.00
reset 19 20 95.00
pwrmgr_reset 1.160s 111.579us 10 10 100.00
pwrmgr_reset_invalid 1.200s 109.998us 9 10 90.00
main_power_glitch_reset 10 10 100.00
pwrmgr_reset 1.160s 111.579us 10 10 100.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.430s 421.079us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.830s 279.936us 10 10 100.00
disable_rom_integrity_check 6 10 60.00
pwrmgr_disable_rom_integrity_check 5.020s 1000.000us 6 10 60.00
stress_all 8 10 80.00
pwrmgr_stress_all 12.850s 10032.020us 8 10 80.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.990s 49.362us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 3.090s 306.430us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 3.090s 306.430us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 1.020s 53.987us 1 1 100.00
pwrmgr_csr_rw 1.010s 46.483us 5 5 100.00
pwrmgr_csr_aliasing 1.230s 50.096us 1 1 100.00
pwrmgr_same_csr_outstanding 1.290s 79.550us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 1.020s 53.987us 1 1 100.00
pwrmgr_csr_rw 1.010s 46.483us 5 5 100.00
pwrmgr_csr_aliasing 1.230s 50.096us 1 1 100.00
pwrmgr_same_csr_outstanding 1.290s 79.550us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
pwrmgr_tl_intg_err 0.980s 9.311us 0 25 0.00
pwrmgr_sec_cm 1.080s 7.082us 0 5 0.00
prim_count_check 0 5 0.00
pwrmgr_sec_cm 1.080s 7.082us 0 5 0.00
prim_fsm_check 0 5 0.00
pwrmgr_sec_cm 1.080s 7.082us 0 5 0.00
sec_cm_bus_integrity 0 25 0.00
pwrmgr_tl_intg_err 0.980s 9.311us 0 25 0.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.740s 1156.418us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 10 10 100.00
pwrmgr_wakeup_reset 1.430s 421.079us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.260s 89.178us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.950s 28.539us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 0 5 0.00
pwrmgr_sec_cm 1.080s 7.082us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
pwrmgr_sec_cm 1.080s 7.082us 0 5 0.00
sec_cm_fsm_terminal 0 5 0.00
pwrmgr_sec_cm 1.080s 7.082us 0 5 0.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.980s 101.932us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 1.060s 43.218us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.660s 221.076us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.010s 46.483us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.010s 46.483us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 6 10 60.00
pwrmgr_escalation_timeout 1.300s 101.030us 6 10 60.00
stress_all_with_rand_reset 10 10 100.00
pwrmgr_stress_all_with_rand_reset 9.260s 6909.883us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 30 test runs
pwrmgr_tl_intg_err 70995702264985427810946505426649560759424941803884676273039516637982971422514 82
UVM_INFO @ 8205355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 17234600191394968141742402668786326046318734871855869149634387239404451161424 78
UVM_INFO @ 7082160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 54477213991156812576225343981486808797634944043165861497000461912885611929363 85
UVM_INFO @ 25522506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 67867074585535502030170996180781216426710619795575956547705402121589408264751 84
UVM_INFO @ 64780652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 114877754781843402863702432825274322465154349891661074889468014738899738134726 78
UVM_INFO @ 10840783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 7576951107964663662682579538855847957965347987273355180551055596149688395731 86
UVM_INFO @ 34816982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 12586660781905508788229122857136646120808029879121506400296756196968360724347 82
UVM_INFO @ 10059773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 86607101461814330506705815928807875453160442319443204995980602279363085426643 79
UVM_INFO @ 21601156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 53297489547496494403506916138579608677306150687178603451146968925054067400077 85
UVM_INFO @ 29439879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 56640042662240555444839070077362019098260227382145308063059624328226659587373 80
UVM_INFO @ 17725058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 89478117062728614431182496268952124923008426188823328022859223772783550830615 78
UVM_INFO @ 9608397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 7784254953948466527075721974536423711691055903938500212984337337032440675685 85
UVM_INFO @ 9357780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 96927988023130986551733622105320828992999949761510511997567980300271487640904 82
UVM_INFO @ 11656942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 17953287661854164236322352610714674768079780663431335602887187598779840412897 78
UVM_INFO @ 8434837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 23551075192680664172336643094735639061243477226985480922488344433396000607484 85
UVM_INFO @ 13003408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 99520314521696983792784361652099386922350635459604740168383355100046526339045 85
UVM_INFO @ 16613226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 3395271527605892014216388943353291119591534150068582496768123796672640394840 78
UVM_INFO @ 13038934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 29326713413379493503761201586097807939106516081947174275557487024628940492576 78
UVM_INFO @ 9594354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 114093175936272284195503798189709296952056445614594576127474723319128337490024 82
UVM_INFO @ 11206177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 44348737651661877519922913724716621024165161231336916760759189590668209160705 82
UVM_INFO @ 9310651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 20879415505189318044170747609729937108696059551617619967113923114337958880470 82
UVM_INFO @ 7468671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 30267739151981589984779056819835397872736458425409806502749402385850746196075 85
UVM_INFO @ 13120440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 6562892938199998057914353286474274206216564301432553994450157587459350170668 78
UVM_INFO @ 13968328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 36484300667523244782445847362652407222395177389276002230982703651827252098412 78
UVM_INFO @ 52499128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 80240633976848900807562812386551264106161299494866172246549171904119180031152 85
UVM_INFO @ 8474383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 100951957351478679331305922712763780174050843608082320082598580922018608440326 85
UVM_INFO @ 7830374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 98185946521739923927246157060366806314035959948138400478477238759019340907850 82
UVM_INFO @ 8875582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 82216631017061790195925256320429343742443711838084513963176465294940335463953 85
UVM_INFO @ 10341303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 100934240627106906089806163173318313031504627048723625897170660978471508025627 85
UVM_INFO @ 7411321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 36133656095646789693914231556856129636376853453664628938193380404169995775237 82
UVM_INFO @ 16262276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 4 test runs
pwrmgr_escalation_timeout 64283825920690559060731628465281493596208429889607599306054460627084108267930 79
UVM_ERROR @ 100607433 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100607433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 19976640446934634435498713336637160759012086795377094409470914420117571623761 79
UVM_ERROR @ 101030264 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101030264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 38410036851662757196708438308225219514554062571928927838267242367380396509458 79
UVM_ERROR @ 159405894 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 159405894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 82541053096044397779246368654111575135024982731138028539501776645670902185409 79
UVM_ERROR @ 401423024 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 401423024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
pwrmgr_disable_rom_integrity_check 110405807893201562752170083087700918643398980745572627552266440623163386621865 110
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 23472686866173180094195475534646324272000623634307813462716119400889239417928 197
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 10779266417068664479189232953029202528673084254780982525166243022326042272230 120
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 2 test runs
pwrmgr_stress_all 29781018392185877379119429533372388068477083556382347393285838883655390628168 396
UVM_INFO @ 11166510947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 43786160587394108382713248734050148382000243557218834566374202057141829572631 117
UVM_INFO @ 10032019548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitStrap 1 test run
pwrmgr_reset_invalid 7575925519425579692319829281037683301498419549702899641693914629461263873134 95
UVM_INFO @ 173376477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwrmgr_scoreboard.sv:259) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * 1 test run
pwrmgr_disable_rom_integrity_check 96872986231523071247041320267697958075067364834371055249316494964180429639941 99
UVM_INFO @ 50629711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---