Simulation Results: rom_ctrl/32kb

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.92%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.100s 418.667us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.780s 566.038us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 6.190s 283.153us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.100s 170.403us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.430s 169.095us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.600s 2217.285us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 6.190s 283.153us 5 5 100.00
rom_ctrl_csr_aliasing 5.430s 169.095us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.900s 212.965us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.930s 2102.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 9.670s 548.395us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 26.310s 2156.058us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.530s 396.354us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 8.690s 3302.247us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 13.300s 552.842us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 13.300s 552.842us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.780s 566.038us 1 1 100.00
rom_ctrl_csr_rw 6.190s 283.153us 5 5 100.00
rom_ctrl_csr_aliasing 5.430s 169.095us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.160s 1221.862us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.780s 566.038us 1 1 100.00
rom_ctrl_csr_rw 6.190s 283.153us 5 5 100.00
rom_ctrl_csr_aliasing 5.430s 169.095us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.160s 1221.862us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 30.080s 589.893us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 288.630s 8243.477us 5 5 100.00
rom_ctrl_tl_intg_err 71.780s 268.579us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 288.630s 8243.477us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 288.630s 8243.477us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 288.630s 8243.477us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 288.630s 8243.477us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.100s 418.667us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.100s 418.667us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.100s 418.667us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 71.780s 268.579us 25 25 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
rom_ctrl_kmac_err_chk 8.530s 396.354us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 194.270s 59246.103us 17 20 85.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 30.080s 589.893us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 288.630s 8243.477us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 308.870s 3722.109us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 99477990291509220601775436830971150743838780377713659269037666138131993606161 104
UVM_INFO @ 1737049555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 22478449950937088781592743066169554529497527586002595257898477979923601541803 78
UVM_INFO @ 714784562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 9798975837511181276503525140097328339606396750201764202839892191728162796183 103
UVM_INFO @ 1511409204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---