Simulation Results: rom_ctrl/64kb

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 13.960s 309.800us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.150s 1595.838us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 9.810s 1873.149us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 11.950s 1025.894us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 11.860s 296.600us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.980s 395.973us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 9.810s 1873.149us 5 5 100.00
rom_ctrl_csr_aliasing 11.860s 296.600us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 17.140s 1065.184us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.980s 377.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 10.380s 249.223us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 47.680s 2730.790us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 21.740s 9868.919us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 17.320s 3403.140us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 18.380s 5527.830us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 18.380s 5527.830us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 11.150s 1595.838us 1 1 100.00
rom_ctrl_csr_rw 9.810s 1873.149us 5 5 100.00
rom_ctrl_csr_aliasing 11.860s 296.600us 1 1 100.00
rom_ctrl_same_csr_outstanding 16.940s 535.141us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 11.150s 1595.838us 1 1 100.00
rom_ctrl_csr_rw 9.810s 1873.149us 5 5 100.00
rom_ctrl_csr_aliasing 11.860s 296.600us 1 1 100.00
rom_ctrl_same_csr_outstanding 16.940s 535.141us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 76.460s 1874.364us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 592.120s 659.792us 5 5 100.00
rom_ctrl_tl_intg_err 188.070s 1736.128us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 592.120s 659.792us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 592.120s 659.792us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 592.120s 659.792us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 592.120s 659.792us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 13.960s 309.800us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 13.960s 309.800us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 13.960s 309.800us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 188.070s 1736.128us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
rom_ctrl_kmac_err_chk 21.740s 9868.919us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 280.130s 10317.233us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 76.460s 1874.364us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 592.120s 659.792us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 399.190s 15361.292us 20 20 100.00