Simulation Results: rstmgr

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.840s 192.413us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.320s 97.580us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.270s 88.448us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.780s 275.691us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.880s 360.166us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.050s 230.957us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.270s 88.448us 5 5 100.00
rstmgr_csr_aliasing 2.880s 360.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 1.420s 206.864us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 3.470s 380.024us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.620s 145.708us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 9.590s 1970.219us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 9.590s 1970.219us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 9.590s 1970.219us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 9.590s 1970.219us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 32.480s 6992.496us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.470s 137.443us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 4.380s 575.368us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 4.380s 575.368us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.320s 97.580us 1 1 100.00
rstmgr_csr_rw 1.270s 88.448us 5 5 100.00
rstmgr_csr_aliasing 2.880s 360.166us 1 1 100.00
rstmgr_same_csr_outstanding 1.750s 156.572us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.320s 97.580us 1 1 100.00
rstmgr_csr_rw 1.270s 88.448us 5 5 100.00
rstmgr_csr_aliasing 2.880s 360.166us 1 1 100.00
rstmgr_same_csr_outstanding 1.750s 156.572us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 26.630s 17199.092us 5 5 100.00
rstmgr_tl_intg_err 4.850s 947.708us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 26.630s 17199.092us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 26.630s 17199.092us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 4.850s 947.708us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.690s 176.245us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 25 25 100.00
rstmgr_leaf_rst_cnsty 12.390s 2459.796us 25 25 100.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 1.770s 302.195us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 26.630s 17199.092us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.270s 88.448us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.270s 88.448us 5 5 100.00