| V1 |
|
100.00% |
| V2 |
|
86.61% |
| V2S |
|
100.00% |
| V3 |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.010s | 296.281us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.960s | 66.238us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.930s | 48.294us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.640s | 140.432us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.200s | 16.263us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.030s | 49.692us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.930s | 48.294us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.200s | 16.263us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 3 | 20 | 15.00 | |||
| rv_timer_random_reset | 11.200s | 8686.538us | 3 | 20 | 15.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 5.640s | 4517.202us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 434.590s | 1104481.957us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 434.590s | 1104481.957us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 8.420s | 8540.632us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.850s | 12.665us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.870s | 12.955us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.120s | 216.940us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.120s | 216.940us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.960s | 66.238us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.930s | 48.294us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.200s | 16.263us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.210s | 44.834us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.960s | 66.238us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.930s | 48.294us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.200s | 16.263us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.210s | 44.834us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.180s | 80.780us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.810s | 452.407us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.810s | 452.407us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 2.270s | 830.367us | 2 | 10 | 20.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.760s | 44.081us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 14 | 20 | 70.00 | |||
| rv_timer_stress_all_with_rand_reset | 49.920s | 28586.753us | 14 | 20 | 70.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 25 test runs | |||
| rv_timer_min | 58962054774230031516620087647276668603907977885557548832077483096507451375241 | 76 |
UVM_INFO @ 231836422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 78267263307076566281213182808098496948717731131389771446574190813573468012336 | 76 |
UVM_INFO @ 1431071749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 73353808112071455815534842878104628480389754825499158230314804335527082681148 | 78 |
UVM_INFO @ 67474845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 6370138787752664249569272833004226130894208746491088184145823372586818991049 | 75 |
UVM_INFO @ 220490352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 25051598857875836338585583725336700293847238217176069412321464383573665936701 | 76 |
UVM_INFO @ 166023675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 45904000657128665479991691887536021150817168073606815487017139785987886525880 | 77 |
UVM_INFO @ 254194476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 45112867397211651317327100636374631453079894161621927519688688657275363810152 | 75 |
UVM_INFO @ 218863191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 29700278924501386116802831244621899712452282910598249225810251452073957502401 | 75 |
UVM_INFO @ 883747394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 85547988417856511705789826493221869513262664653970450308457694103116868404494 | 75 |
UVM_INFO @ 209478683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 63168040659123623648832790003750451531263672523750976741514391693689791164949 | 76 |
UVM_INFO @ 232128913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 104451304923372833396131574352459345599862389369801342613241667877584491972196 | 78 |
UVM_INFO @ 229906132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 47364289901402105639235805670166791884013162111258762612699899279996748027437 | 75 |
UVM_INFO @ 238898398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 19340070383922527449652273601005476629837468984444897856669954384204001413411 | 76 |
UVM_INFO @ 627655009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 3391961677533514143443052582749024398474092011949745442534057625566830785290 | 75 |
UVM_INFO @ 1664247610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 32248524449501064929982244437726856714222968262910790851139903966157226196167 | 75 |
UVM_INFO @ 64135499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 51059979385381792416691389831522144460709084516520838514103428181921817274192 | 75 |
UVM_INFO @ 336785960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 71527530938371178658822384875458342479962179879602929100117195229150494504590 | 75 |
UVM_INFO @ 643142081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85237978142555563958797683580530734650328742040072866306334579929162735244827 | 75 |
UVM_INFO @ 91520037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 27719569723129391498876172570568503204824126041422093691737268445393674891575 | 75 |
UVM_INFO @ 174241212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 29396448197547362699547775869907151227228002426493761389292242918287148496065 | 75 |
UVM_INFO @ 397283455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 54507480420440392752383975937981461301852809082315523300470077243766117405940 | 77 |
UVM_INFO @ 8686537717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 99397360134641743210225234295123807060099719121253296031652697675126841757147 | 75 |
UVM_INFO @ 1065609232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 65738411528148299351439519930728253824847973836485636238073327901393163774889 | 75 |
UVM_INFO @ 78839393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 43008850179718217612436979297547680782828548668402582389710792597096174065054 | 76 |
UVM_INFO @ 152347385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 6142813153290691636439736433307922949956630799535394655009449467946292911192 | 75 |
UVM_INFO @ 116647664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 8 test runs | |||
| rv_timer_max | 6473087110334695080899506792217649346199369783572725444744436291646899971798 | 75 |
UVM_INFO @ 636296863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 105543790831785398343265991011197169789292032300925326646775252926852849474925 | 75 |
UVM_INFO @ 42285781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 44293399463579706666177213752203917903101370780953289239791084744925532842146 | 75 |
UVM_INFO @ 49305821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 24704986187556127826364864601600837841192020384881293766822741379368590225906 | 75 |
UVM_INFO @ 45437291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 44753910695227598167433030454609976974234279562723668579525593856276511241677 | 75 |
UVM_INFO @ 49726881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 89498191790006954994197455704506242392994538701069326644093515412139620861299 | 75 |
UVM_INFO @ 173614494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 3732234629026021795072355930650187482237928878009717927778132310305202382229 | 75 |
UVM_INFO @ 43502177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 51057607719426519959620888165763712268486268737489581598472296397654483777473 | 75 |
UVM_INFO @ 163370825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 3 test runs | |||
| rv_timer_stress_all_with_rand_reset | 42854439460130708415824620297415304772684295719013640799254162277089119890103 | 423 |
UVM_INFO @ 27517840819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 73579418805770496237596198694501453193010297013486601959994586412154484619965 | 98 |
UVM_INFO @ 3340614085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 4753508459208767287112551993488350986580192011226653516723254196439580119038 | 104 |
UVM_INFO @ 12003867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | 3 test runs | |||
| rv_timer_stress_all_with_rand_reset | 3190446619808201776698841194419645921235574457952567764503347228320472495859 | 327 |
UVM_INFO @ 7038189200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 72086450821391732980861604620057543567478721459682769250291088934738996919453 | 313 |
UVM_INFO @ 8407369118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 71078008527216771053008451785414328558857252973474322166882611592072610295308 | 386 |
UVM_INFO @ 28586752982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | 2 test runs | |||
| rv_timer_max | 8174752803737762005780721442062791180631691382857024624467271280580829211401 | 75 |
UVM_INFO @ 41925267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 15215631161140297782381081785190240050925925474840761787311276266651866917200 | 75 |
UVM_INFO @ 44081409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|