Simulation Results: spi_device/2p

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 94.21 %
  • assert
  • 94.62 %
  • func
  • 98.56 %
  • line
  • 98.95 %
  • branch
  • 98.37 %
  • cond
  • 96.61 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
96.00%
V2
99.62%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 9 10 90.00
spi_device_flash_and_tpm 293.960s 39602.780us 9 10 90.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.360s 157.004us 1 1 100.00
csr_rw 5 5 100.00
spi_device_csr_rw 2.980s 320.031us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 21.690s 3348.175us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 22.690s 7564.508us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_device_csr_mem_rw_with_rand_reset 4.300s 275.461us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_device_csr_rw 2.980s 320.031us 5 5 100.00
spi_device_csr_aliasing 22.690s 7564.508us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.050s 39.415us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.730s 17.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 10 10 100.00
spi_device_csb_read 1.240s 38.492us 10 10 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.590s 27.535us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.150s 17.157us 1 1 100.00
tpm_read 10 10 100.00
spi_device_tpm_rw 3.880s 536.385us 10 10 100.00
tpm_write 10 10 100.00
spi_device_tpm_rw 3.880s 536.385us 10 10 100.00
tpm_hw_reg 20 20 100.00
spi_device_tpm_read_hw_reg 14.480s 11198.283us 10 10 100.00
spi_device_tpm_sts_read 1.370s 75.071us 10 10 100.00
tpm_fully_random_case 10 10 100.00
spi_device_tpm_all 23.530s 3653.721us 10 10 100.00
pass_cmd_filtering 20 20 100.00
spi_device_pass_cmd_filtering 54.200s 81739.155us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
pass_addr_translation 20 20 100.00
spi_device_pass_addr_payload_swap 17.330s 11027.178us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
pass_payload_translation 20 20 100.00
spi_device_pass_addr_payload_swap 17.330s 11027.178us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
cmd_info_slots 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
cmd_read_status 20 20 100.00
spi_device_intercept 26.710s 3023.966us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
cmd_read_jedec 20 20 100.00
spi_device_intercept 26.710s 3023.966us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
cmd_read_sfdp 20 20 100.00
spi_device_intercept 26.710s 3023.966us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
cmd_fast_read 20 20 100.00
spi_device_intercept 26.710s 3023.966us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
cmd_read_pipeline 20 20 100.00
spi_device_intercept 26.710s 3023.966us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
flash_cmd_upload 10 10 100.00
spi_device_upload 42.000s 75903.076us 10 10 100.00
mailbox_command 10 10 100.00
spi_device_mailbox 74.320s 26512.502us 10 10 100.00
mailbox_cross_outside_command 10 10 100.00
spi_device_mailbox 74.320s 26512.502us 10 10 100.00
mailbox_cross_inside_command 10 10 100.00
spi_device_mailbox 74.320s 26512.502us 10 10 100.00
cmd_read_buffer 20 20 100.00
spi_device_flash_mode 43.010s 24435.052us 10 10 100.00
spi_device_read_buffer_direct 8.420s 830.877us 10 10 100.00
cmd_dummy_cycle 20 20 100.00
spi_device_mailbox 74.320s 26512.502us 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
quad_spi 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
dual_spi 10 10 100.00
spi_device_flash_all 369.320s 55314.010us 10 10 100.00
4b_3b_feature 10 10 100.00
spi_device_cfg_cmd 9.950s 2228.978us 10 10 100.00
write_enable_disable 10 10 100.00
spi_device_cfg_cmd 9.950s 2228.978us 10 10 100.00
TPM_with_flash_or_passthrough_mode 9 10 90.00
spi_device_flash_and_tpm 293.960s 39602.780us 9 10 90.00
tpm_and_flash_trans_with_min_inactive_time 25 25 100.00
spi_device_flash_and_tpm_min_idle 415.100s 56609.908us 25 25 100.00
stress_all 10 10 100.00
spi_device_stress_all 614.620s 333058.950us 10 10 100.00
alert_test 10 10 100.00
spi_device_alert_test 1.150s 12.948us 10 10 100.00
intr_test 10 10 100.00
spi_device_intr_test 1.190s 47.951us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_device_tl_errors 6.630s 264.943us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_device_tl_errors 6.630s 264.943us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_device_csr_hw_reset 1.360s 157.004us 1 1 100.00
spi_device_csr_rw 2.980s 320.031us 5 5 100.00
spi_device_csr_aliasing 22.690s 7564.508us 1 1 100.00
spi_device_same_csr_outstanding 5.210s 625.930us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_device_csr_hw_reset 1.360s 157.004us 1 1 100.00
spi_device_csr_rw 2.980s 320.031us 5 5 100.00
spi_device_csr_aliasing 22.690s 7564.508us 1 1 100.00
spi_device_same_csr_outstanding 5.210s 625.930us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_device_sec_cm 2.110s 5557.887us 5 5 100.00
spi_device_tl_intg_err 23.860s 1036.020us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
spi_device_tl_intg_err 23.860s 1036.020us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_device_flash_mode_ignore_cmds 350.570s 65051.299us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp * 1 test run
spi_device_flash_and_tpm 4223578836812367308784222238033923346039032992246712491121100882820149058437 126
tl_ul_fuzzy_flash_status_q[i] = 0x6ecfc
UVM_INFO @ 37360676107 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 10/10
tl_ul_fuzzy_flash_status_q[i] = 0xdea85a
tl_ul_fuzzy_flash_status_q[i] = 0x33c222