Simulation Results: sram_ctrl/main

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.56 %
  • code
  • 96.63 %
  • assert
  • 96.46 %
  • func
  • 96.60 %
  • block
  • 95.95 %
  • line
  • 96.59 %
  • branch
  • 93.84 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 11.000s 8312.736us 5 5 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 15.618us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 39.595us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 123.432us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 85.355us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.000s 3240.483us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 39.595us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 85.355us 1 1 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 254.000s 28762.761us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 135.000s 22209.562us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 45.000s 10011.582us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 274.000s 5242.343us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 199.000s 24529.154us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 87.000s 49685.646us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 66.000s 60763.739us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 65.000s 32614.466us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 9.000s 5528.854us 5 5 100.00
sram_ctrl_partial_access_b2b 337.000s 40781.714us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 8.000s 1361.360us 5 5 100.00
sram_ctrl_throughput_w_partial_write 7.000s 719.863us 5 5 100.00
sram_ctrl_throughput_w_readback 8.000s 3163.987us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 21.000s 5861.551us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 4.000s 935.015us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 646.000s 100686.816us 5 5 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 21.989us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 387.176us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 387.176us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 15.618us 1 1 100.00
sram_ctrl_csr_rw 2.000s 39.595us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 85.355us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 12.306us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 15.618us 1 1 100.00
sram_ctrl_csr_rw 2.000s 39.595us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 85.355us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 12.306us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 37.000s 29391.596us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 6.000s 4553.369us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 334.193us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 4553.369us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 334.193us 25 25 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 21.000s 5861.551us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 21.000s 5861.551us 5 5 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 39.595us 5 5 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 65.000s 32614.466us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 65.000s 32614.466us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 65.000s 32614.466us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 66.000s 60763.739us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 8.000s 711.684us 5 5 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 37.000s 29391.596us 5 5 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 8.000s 2762.511us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 11.000s 8312.736us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 11.000s 8312.736us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 65.000s 32614.466us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 4553.369us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 66.000s 60763.739us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 4553.369us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 4553.369us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 11.000s 8312.736us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 4553.369us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 5 80.00
sram_ctrl_stress_all_with_rand_reset 52.000s 1366.495us 4 5 80.00

Error Messages

   Test seed line log context
UVM_ERROR (tl_host_driver.sv:119) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 4599220040458746296750786690298429134206745222265958168294705763648910438822 105
UVM_INFO @ 201388505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---