Simulation Results: sram_ctrl/ret

 
15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.15 %
  • code
  • 83.42 %
  • assert
  • 96.43 %
  • func
  • 96.60 %
  • block
  • 93.87 %
  • line
  • 95.04 %
  • branch
  • 89.67 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 2.000s 92.826us 5 5 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.149us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.030us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 122.267us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.408us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 45.848us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 18.030us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 23.408us 1 1 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 14.000s 686.439us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 7.000s 683.654us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 10.000s 1301.125us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 215.000s 27499.736us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 9.000s 330.597us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 22.000s 1407.898us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 12.000s 2659.338us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 17.000s 3843.686us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 2.000s 33.208us 5 5 100.00
sram_ctrl_partial_access_b2b 280.000s 15800.423us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 143.318us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 130.086us 5 5 100.00
sram_ctrl_throughput_w_readback 3.000s 43.879us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 17.000s 2984.910us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 86.052us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 56.000s 14440.012us 5 5 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 24.241us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 1916.019us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 1916.019us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 13.149us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.030us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 23.408us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.770us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 13.149us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.030us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 23.408us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.770us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 304.081us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 6.000s 666.509us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 1517.671us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 666.509us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 1517.671us 25 25 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 17.000s 2984.910us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 17.000s 2984.910us 5 5 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.030us 5 5 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 17.000s 3843.686us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 17.000s 3843.686us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 17.000s 3843.686us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 12.000s 2659.338us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 211.251us 5 5 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 304.081us 5 5 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 47.348us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 92.826us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 92.826us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 17.000s 3843.686us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 666.509us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 12.000s 2659.338us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 666.509us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 666.509us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 2.000s 92.826us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 666.509us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 49.000s 1008.701us 5 5 100.00