Simulation Results

Simulation Results: sysrst_ctrl

15/05/2026 15:00:24 DVSim: v1.34.0 sha: 9b0af25 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
93.63 %

code
98.01 %

assert
97.80 %

func
85.08 %

line
99.29 %

branch
99.33 %

cond
97.86 %

toggle
100.00 %

FSM
93.59 %

Validation stages

V1		100.00%
V2		97.04%
V2S		100.00%
V3		100.00%

43/43 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	sysrst_ctrl_smoke	7.960s	2108.289us	10	10	100.00
input_output_inverted				10	10	100.00
	sysrst_ctrl_in_out_inverted	9.970s	2440.032us	10	10	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	9.110s	2418.474us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	8.910s	2312.825us	5	5	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	2.410s	4049.155us	1	1	100.00
csr_rw				5	5	100.00
	sysrst_ctrl_csr_rw	8.000s	2035.425us	5	5	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	119.860s	76134.249us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	7.920s	2588.673us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	8.880s	2041.259us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sysrst_ctrl_csr_rw	8.000s	2035.425us	5	5	100.00
	sysrst_ctrl_csr_aliasing	7.920s	2588.673us	1	1	100.00

295/304 passed

97.04 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				10	10	100.00
	sysrst_ctrl_combo_detect	443.950s	168695.488us	10	10	100.00
combo_detect_with_pre_cond				92	100	92.00
	sysrst_ctrl_combo_detect_with_pre_cond	297.420s	164977.105us	92	100	92.00
auto_block_key_outputs				25	25	100.00
	sysrst_ctrl_auto_blk_key_output	284.330s	250598.376us	25	25	100.00
keyboard_input_triggered_interrupt				50	50	100.00
	sysrst_ctrl_edge_detect	1010.050s	1700973.263us	50	50	100.00
pin_output_keyboard_inversion_control				10	10	100.00
	sysrst_ctrl_pin_override_test	6.550s	2511.708us	10	10	100.00
pin_input_value_accessibility				10	10	100.00
	sysrst_ctrl_pin_access_test	8.560s	2244.974us	10	10	100.00
ec_power_on_reset				10	10	100.00
	sysrst_ctrl_ec_pwr_on_rst	148.770s	232555.283us	10	10	100.00
flash_write_protect_output				10	10	100.00
	sysrst_ctrl_flash_wr_prot_out	9.260s	2611.518us	10	10	100.00
ultra_low_power_test				9	10	90.00
	sysrst_ctrl_ultra_low_pwr	359.170s	3859743.597us	9	10	90.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	60.660s	40968.085us	2	2	100.00
stress_all				10	10	100.00
	sysrst_ctrl_stress_all	464.460s	205125.607us	10	10	100.00
alert_test				10	10	100.00
	sysrst_ctrl_alert_test	7.590s	2012.193us	10	10	100.00
intr_test				10	10	100.00
	sysrst_ctrl_intr_test	8.260s	2013.425us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	sysrst_ctrl_tl_errors	10.740s	2134.098us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	sysrst_ctrl_tl_errors	10.740s	2134.098us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	2.410s	4049.155us	1	1	100.00
	sysrst_ctrl_csr_rw	8.000s	2035.425us	5	5	100.00
	sysrst_ctrl_csr_aliasing	7.920s	2588.673us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	21.930s	5066.352us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	2.410s	4049.155us	1	1	100.00
	sysrst_ctrl_csr_rw	8.000s	2035.425us	5	5	100.00
	sysrst_ctrl_csr_aliasing	7.920s	2588.673us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	21.930s	5066.352us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	sysrst_ctrl_sec_cm	103.280s	42011.893us	5	5	100.00
	sysrst_ctrl_tl_intg_err	156.460s	42503.181us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	sysrst_ctrl_tl_intg_err	156.460s	42503.181us	25	25	100.00

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				10	10	100.00
	sysrst_ctrl_stress_all_with_rand_reset	24.990s	5670.570us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])				3 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	78463475736485124470526946641834489468896137274194588432701935590644332259568	701	UVM_INFO @ 51815500781 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 51835500781 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 62117978941 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32 UVM_INFO @ 62118096589 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25
	sysrst_ctrl_combo_detect_with_pre_cond	97190111574249508575787149377663301194633725689944889773538235092425945641656	680	UVM_ERROR @ 50493176040 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 50493176040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	44560737181066073726878303723612009002595402835659534759659674339009735653807	692	UVM_INFO @ 52032532418 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 52052532418 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_ERROR @ 52062643886 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (2 [0x2] vs 10 [0xa]) UVM_INFO @ 52062643886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				1 test run
	sysrst_ctrl_ultra_low_pwr	77899771764791060740025077297473062669236938686217246927757975152457194255162	657	UVM_INFO @ 178980924288 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 2425860924288 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 3532920924288 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 3532949804749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	42449298898175160718907826881959005616445763165128867144747031158468908755485	667	UVM_ERROR @ 12802671947 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4 UVM_INFO @ 12802671947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	98693390667521553935427311008393077716314760468109800787639634723157077033773	695	UVM_INFO @ 38135686980 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :0 UVM_INFO @ 38135686980 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :2 UVM_ERROR @ 38135686980 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 38135686980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	94131616876611682239371750176793676147585587329272684344834788636125204584556	665	UVM_INFO @ 25843665365 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x26 UVM_INFO @ 25844198701 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x24 UVM_INFO @ 26285067572 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2 UVM_INFO @ 26299116440 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 16
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	61911521011942539123908834299960411123337177743077699937077401883434653005814	668	UVM_INFO @ 14027800372 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 14047800372 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 24174516609 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32 UVM_INFO @ 24174596609 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x17
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	17740001651617898918687854235807858979184242702728128183500628707900314452904	665	UVM_INFO @ 15554870653 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 15569870653 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1d UVM_INFO @ 20170524816 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1 UVM_INFO @ 20184870653 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 3