Simulation Results: adc_ctrl

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.32 %
  • code
  • 92.10 %
  • assert
  • 90.92 %
  • func
  • 12.94 %
  • line
  • 98.00 %
  • branch
  • 96.23 %
  • cond
  • 85.44 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.050s 5920.212us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.240s 1052.329us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.500s 381.283us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 77.790s 26523.438us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.330s 1026.150us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.790s 500.666us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.500s 381.283us 1 1 100.00
adc_ctrl_csr_aliasing 2.330s 1026.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.900s 347.191us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.130s 298.703us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.260s 313.632us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.710s 421.368us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.020s 459.017us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.880s 446.041us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.370s 365.772us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.810s 458.893us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.120s 4152.863us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 14.140s 24776.310us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 149.000s 75691.235us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.580s 669.682us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 2.090s 391.023us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.380s 365.063us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.830s 557.985us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.830s 557.985us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.240s 1052.329us 1 1 100.00
adc_ctrl_csr_rw 1.500s 381.283us 1 1 100.00
adc_ctrl_csr_aliasing 2.330s 1026.150us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.480s 1864.512us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.240s 1052.329us 1 1 100.00
adc_ctrl_csr_rw 1.500s 381.283us 1 1 100.00
adc_ctrl_csr_aliasing 2.330s 1026.150us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.480s 1864.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.850s 8416.165us 1 1 100.00
adc_ctrl_tl_intg_err 8.720s 4181.286us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 8.720s 4181.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.360s 999.759us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 67885239886478455103259407591454006536181306892644842942972351471245452008839 388
UVM_INFO @ 347191161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 30216443458000078588516185506764465491798765661715644853169632804631167005756 388
UVM_INFO @ 298702976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 111668858094218563638570163229370965755112712895054879371585906643376349361882 388
UVM_INFO @ 313632433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 38161925163678063255341296766687157980632992541390225008151644851503250441494 388
UVM_INFO @ 421368220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 15755001533540527745850486504393117602021196184697736178753935284111446451937 388
UVM_INFO @ 459016787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 65717630170750880117593856371169246438973672498206385612357540486176954534558 388
UVM_INFO @ 446041042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 73862493470333377556071302596198182563048408349206820397337662393364082885500 388
UVM_INFO @ 458892673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 57266008754016014012052185320221462750915928211202968306260917601138925918367 388
UVM_INFO @ 365771729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 67264713940047273002682897696897582117311731844598634833744565921053556334882 401
UVM_INFO @ 999758528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 80205578996446261777071453265649385991370282111275155111527778602057339333451 389
UVM_INFO @ 669682241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---