Simulation Results: aes/masked

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.41 %
  • code
  • 94.29 %
  • assert
  • 98.23 %
  • func
  • 78.72 %
  • block
  • 94.45 %
  • line
  • 96.07 %
  • branch
  • 87.54 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 121.216us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 77.831us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 85.913us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 115.239us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 118.381us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 226.549us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 100.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 115.239us 1 1 100.00
aes_csr_aliasing 4.000s 226.549us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 77.831us 1 1 100.00
aes_config_error 10.000s 1155.402us 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 77.831us 1 1 100.00
aes_config_error 10.000s 1155.402us 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 194.601us 1 1 100.00
aes_b2b 10.000s 474.425us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 77.831us 1 1 100.00
aes_config_error 10.000s 1155.402us 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
aes_alert_reset 12.000s 1975.976us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 117.120us 1 1 100.00
aes_config_error 10.000s 1155.402us 1 1 100.00
aes_alert_reset 12.000s 1975.976us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 113.488us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 598.974us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 12.000s 1975.976us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 194.601us 1 1 100.00
aes_sideload 3.000s 70.367us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 150.454us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 43.000s 2767.538us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 59.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 666.070us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 666.070us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 85.913us 1 1 100.00
aes_csr_rw 1.000s 115.239us 1 1 100.00
aes_csr_aliasing 4.000s 226.549us 1 1 100.00
aes_same_csr_outstanding 3.000s 161.857us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 85.913us 1 1 100.00
aes_csr_rw 1.000s 115.239us 1 1 100.00
aes_csr_aliasing 4.000s 226.549us 1 1 100.00
aes_same_csr_outstanding 3.000s 161.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 400.936us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 120.554us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 120.554us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 120.554us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 120.554us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 114.888us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 493.174us 1 1 100.00
aes_tl_intg_err 2.000s 356.018us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 356.018us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 12.000s 1975.976us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 120.554us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 120.554us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 77.831us 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
aes_alert_reset 12.000s 1975.976us 1 1 100.00
aes_core_fi 3.000s 119.626us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 10.000s 1155.402us 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
aes_core_fi 3.000s 119.626us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 120.554us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 55.777us 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 194.601us 1 1 100.00
aes_sideload 3.000s 70.367us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.777us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.777us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 55.777us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 55.777us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 55.777us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 194.601us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 168.909us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
aes_ctr_fi 3.000s 85.686us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 168.909us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 168.909us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_ctr_fi 3.000s 85.686us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 168.909us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
aes_ctr_fi 3.000s 85.686us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 12.000s 1975.976us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
aes_ctr_fi 3.000s 85.686us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
aes_ctr_fi 3.000s 85.686us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_ctr_fi 3.000s 85.686us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 4.000s 168.909us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 4.000s 168.909us 1 1 100.00
aes_control_fi 3.000s 62.645us 1 1 100.00
aes_cipher_fi 3.000s 54.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 35.000s 864.441us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
aes_stress_all_with_rand_reset 23648554388175845051732600762114752356223771577429045494179512305270501716417 1017
UVM_INFO @ 864441403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---