Simulation Results

Simulation Results: chip

20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
74.81 %

code
84.97 %

assert
97.37 %

func
42.08 %

line
94.26 %

branch
93.61 %

cond
88.68 %

toggle
91.16 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		77.34%
V2S		100.00%
V3		65.38%
unmapped		72.73%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	115.920s	2683.498us	1	1	100.00
	chip_sw_example_rom	139.370s	3253.009us	1	1	100.00
	chip_sw_example_manufacturer	178.750s	2423.834us	1	1	100.00
	chip_sw_example_concurrency	188.410s	3033.754us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	170.980s	4407.235us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	362.580s	5937.955us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2815.150s	31674.841us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4429.520s	27747.927us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	65.210s	2316.565us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4429.520s	27747.927us	1	1	100.00
	chip_csr_rw	362.580s	5937.955us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	7.990s	51.411us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	372.450s	4436.719us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	372.450s	4436.719us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	372.450s	4436.719us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	486.150s	4148.394us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	486.150s	4148.394us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	466.560s	4266.993us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	556.590s	4416.038us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	491.870s	4321.730us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1467.190s	8431.186us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1374.880s	8573.365us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	852.690s	8870.398us	1	1	100.00

215/278 passed

77.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	183.470s	3912.507us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	183.470s	3912.507us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	283.080s	3272.801us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	307.790s	5443.860us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	212.160s	3545.838us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	520.650s	6699.041us	1	1	100.00
	chip_tap_straps_testunlock0	191.340s	4280.828us	1	1	100.00
	chip_tap_straps_rma	364.980s	5443.426us	1	1	100.00
	chip_tap_straps_prod	128.530s	2689.109us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	168.590s	2717.991us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	1087.740s	8832.344us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	564.690s	5647.990us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	564.690s	5647.990us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	700.250s	7302.719us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	818.130s	10032.374us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	491.100s	4254.678us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	774.920s	6039.573us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4546.520s	19460.988us	1	1	100.00
	chip_sw_aes_enc_jitter_en	186.850s	3309.452us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	794.300s	6550.620us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	236.440s	3064.900us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1814.470s	11649.490us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	264.030s	3442.942us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	472.590s	5099.845us	1	1	100.00
	chip_sw_clkmgr_jitter	215.870s	3774.624us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	307.160s	3516.292us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	528.560s	6240.609us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	314.190s	4872.904us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	201.360s	3565.639us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	314.190s	4872.904us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	160.620s	3199.915us	1	1	100.00
	chip_sw_aes_smoketest	190.030s	2645.703us	1	1	100.00
	chip_sw_aon_timer_smoketest	261.660s	3340.707us	1	1	100.00
	chip_sw_clkmgr_smoketest	187.020s	2532.001us	1	1	100.00
	chip_sw_csrng_smoketest	205.760s	2915.763us	1	1	100.00
	chip_sw_entropy_src_smoketest	1028.850s	6254.250us	1	1	100.00
	chip_sw_gpio_smoketest	291.550s	3803.175us	1	1	100.00
	chip_sw_hmac_smoketest	262.610s	3454.545us	1	1	100.00
	chip_sw_kmac_smoketest	269.060s	2910.453us	1	1	100.00
	chip_sw_otbn_smoketest	1158.100s	7490.754us	1	1	100.00
	chip_sw_pwrmgr_smoketest	495.640s	6150.278us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	337.800s	5981.755us	1	1	100.00
	chip_sw_rv_plic_smoketest	193.860s	2721.649us	1	1	100.00
	chip_sw_rv_timer_smoketest	209.160s	2895.412us	1	1	100.00
	chip_sw_rstmgr_smoketest	212.300s	3423.063us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	198.060s	2843.131us	1	1	100.00
	chip_sw_uart_smoketest	186.620s	2663.709us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	212.140s	3216.432us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	503.850s	5809.166us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8592.520s	62871.090us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3933.130s	15537.582us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	73.646s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	234.920s	3930.550us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	247.260s	2503.430us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7784.260s	55708.881us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	8167.610s	57943.088us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	59.230s	2156.840us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	59.230s	2156.840us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4429.520s	27747.927us	1	1	100.00
	chip_same_csr_outstanding	2711.880s	29367.617us	1	1	100.00
	chip_csr_hw_reset	170.980s	4407.235us	1	1	100.00
	chip_csr_rw	362.580s	5937.955us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4429.520s	27747.927us	1	1	100.00
	chip_same_csr_outstanding	2711.880s	29367.617us	1	1	100.00
	chip_csr_hw_reset	170.980s	4407.235us	1	1	100.00
	chip_csr_rw	362.580s	5937.955us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	25.170s	928.679us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	7.330s	45.467us	1	1	100.00
	xbar_smoke_large_delays	83.740s	7700.839us	1	1	100.00
	xbar_smoke_slow_rsp	76.820s	5437.809us	1	1	100.00
	xbar_random_zero_delays	39.930s	436.686us	1	1	100.00
	xbar_random_large_delays	455.100s	55699.374us	1	1	100.00
	xbar_random_slow_rsp	143.340s	13002.963us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	26.090s	242.017us	1	1	100.00
	xbar_error_and_unmapped_addr	11.260s	168.225us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	42.080s	466.550us	1	1	100.00
	xbar_error_and_unmapped_addr	11.260s	168.225us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	55.310s	1647.824us	1	1	100.00
	xbar_access_same_device_slow_rsp	815.710s	69335.651us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	33.090s	1143.577us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	343.210s	4846.601us	1	1	100.00
	xbar_stress_all_with_error	401.140s	13686.989us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	365.980s	9132.636us	1	1	100.00
	xbar_stress_all_with_reset_error	171.270s	543.844us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3933.130s	15537.582us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3537.460s	33581.951us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3843.670s	15749.575us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	62.073s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	294.161s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	103.175s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	70.067s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	67.126s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	213.543s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	120.900s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	138.357s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	128.545s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	107.652s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	73.680s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.584s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	129.080s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.739s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	21.987s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	264.950s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	36.355s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	220.451s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	14.162s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	195.283s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	166.760s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	47.960s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	21.264s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	99.840s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	49.031s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	335.993s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.268s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	41.086s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.272s	0.000us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	68.411s	0.000us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	182.849s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	17.680s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	145.976s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	136.201s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	175.082s	0.000us	0	1	0.00
rom_e2e_keymgr_init				1	3	33.33
	rom_e2e_keymgr_init_rom_ext_meas	3683.410s	15465.906us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6212.130s	28985.762us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	3825.950s	17420.493us	0	1	0.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3940.460s	17121.971us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.165s	0.000us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.165s	0.000us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	251.280s	2607.602us	1	1	100.00
	chip_sw_aes_enc_jitter_en	186.850s	3309.452us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	166.440s	2439.467us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	266.540s	2947.689us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	897.780s	7862.284us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	246.000s	3061.501us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	465.660s	5548.037us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	474.000s	4947.788us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	706.050s	5296.375us	1	1	100.00
	chip_plic_all_irqs_10	390.000s	3387.470us	1	1	100.00
	chip_plic_all_irqs_20	489.410s	4806.815us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	266.040s	3273.623us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1363.890s	12442.448us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	391.170s	4277.328us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	148.730s	2895.961us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.154s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1524.210s	9351.499us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	817.380s	6481.461us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	1074.000s	8290.528us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9258.650s	255593.301us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	322.490s	4262.168us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	495.640s	6150.278us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	322.490s	4262.168us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	518.760s	8020.444us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	518.760s	8020.444us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	410.170s	7264.915us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	456.210s	5039.364us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	798.770s	6013.703us	1	1	100.00
	chip_sw_aes_idle	266.540s	2947.689us	1	1	100.00
	chip_sw_hmac_enc_idle	203.060s	2826.686us	1	1	100.00
	chip_sw_kmac_idle	237.390s	3199.172us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	332.390s	5389.573us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	371.280s	4805.374us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	365.450s	4224.946us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	290.400s	4527.144us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	908.150s	9743.125us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	506.220s	4732.574us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	561.120s	4645.857us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	462.430s	3711.253us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	479.580s	4567.117us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	576.910s	4143.101us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	490.360s	4982.100us	1	1	100.00
	chip_sw_ast_clk_outputs	700.250s	7302.719us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	825.200s	9499.342us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	462.430s	3711.253us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	479.580s	4567.117us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	491.100s	4254.678us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	774.920s	6039.573us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4546.520s	19460.988us	1	1	100.00
	chip_sw_aes_enc_jitter_en	186.850s	3309.452us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	794.300s	6550.620us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	236.440s	3064.900us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1814.470s	11649.490us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	264.030s	3442.942us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	472.590s	5099.845us	1	1	100.00
	chip_sw_clkmgr_jitter	215.870s	3774.624us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	172.180s	2474.480us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	469.970s	4619.516us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	814.110s	7217.563us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4556.160s	25328.978us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	235.270s	2959.856us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	195.090s	3160.766us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	774.500s	7774.355us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	253.090s	4033.941us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	413.970s	5051.774us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1620.740s	22791.472us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	3909.170s	21600.313us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	700.250s	7302.719us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	432.390s	4817.678us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	351.760s	3462.072us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	474.000s	4947.788us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1524.210s	9351.499us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2946.000s	24579.441us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	172.840s	3634.318us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	592.110s	8380.328us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	238.550s	3188.460us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	4933.750s	22524.373us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	164.690s	3265.983us	1	1	100.00
	chip_sw_edn_entropy_reqs	1156.220s	7696.570us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	164.690s	3265.983us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2946.000s	24579.441us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	193.260s	3123.739us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1407.570s	22160.584us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	825.570s	5333.745us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	774.920s	6039.573us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	441.840s	3547.381us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	491.100s	4254.678us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	4736.760s	44854.712us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1407.570s	22160.584us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	216.630s	3530.484us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1747.520s	9551.970us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.580s	2611.654us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	4736.760s	44854.712us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.580s	2611.654us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.580s	2611.654us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.580s	2611.654us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.580s	2611.654us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	474.000s	4947.788us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	254.270s	10978.333us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	685.100s	4789.629us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	502.760s	5839.284us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	502.760s	5839.284us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	260.480s	3022.962us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	236.440s	3064.900us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	203.060s	2826.686us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1244.500s	8019.998us	1	1	100.00
chip_sw_hmac_multistream_mode				1	1	100.00
	chip_sw_hmac_multistream	893.080s	6141.572us	1	1	100.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	514.990s	5087.528us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	552.500s	5634.751us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	483.220s	4935.505us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	344.290s	4389.489us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1747.520s	9551.970us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1814.470s	11649.490us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	2232.710s	12653.665us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	897.780s	7862.284us	1	1	100.00
chip_sw_keymgr_sideload_otbn				1	1	100.00
	chip_sw_keymgr_sideload_otbn	3394.240s	16544.195us	1	1	100.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	219.910s	3471.641us	1	1	100.00
	chip_sw_kmac_mode_kmac	245.250s	2635.676us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	264.030s	3442.942us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1747.520s	9551.970us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	178.330s	2819.867us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1895.970s	10605.044us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	237.390s	3199.172us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	465.660s	5548.037us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	520.650s	6699.041us	1	1	100.00
	chip_tap_straps_rma	364.980s	5443.426us	1	1	100.00
	chip_tap_straps_prod	128.530s	2689.109us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	163.310s	2475.028us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1394.310s	8557.032us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	214.580s	2611.654us	0	1	0.00
	chip_sw_flash_rma_unlocked	4736.760s	44854.712us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	249.220s	2745.583us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	584.330s	7228.393us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	628.600s	5465.167us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	689.260s	7046.938us	0	1	0.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
	chip_sw_keymgr_key_derivation	1747.520s	9551.970us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	440.630s	10464.750us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	774.560s	8964.534us	1	1	100.00
	chip_prim_tl_access	254.270s	10978.333us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	825.200s	9499.342us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	506.220s	4732.574us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	561.120s	4645.857us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	462.430s	3711.253us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	479.580s	4567.117us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	576.910s	4143.101us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	490.360s	4982.100us	1	1	100.00
	chip_tap_straps_dev	520.650s	6699.041us	1	1	100.00
	chip_tap_straps_rma	364.980s	5443.426us	1	1	100.00
	chip_tap_straps_prod	128.530s	2689.109us	1	1	100.00
	chip_rv_dm_lc_disabled	44.560s	2098.324us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	175.860s	3661.648us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	132.720s	2976.216us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	109.900s	3468.586us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	261.280s	3050.772us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	2177.500s	34371.717us	1	1	100.00
	chip_rv_dm_lc_disabled	44.560s	2098.324us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	933.300s	10465.569us	0	1	0.00
	chip_sw_lc_walkthrough_prod	818.380s	10880.201us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	932.980s	8788.401us	1	1	100.00
	chip_sw_lc_walkthrough_rma	351.170s	7511.025us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	2177.500s	34371.717us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	98.350s	2378.625us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	104.920s	2928.816us	1	1	100.00
	rom_volatile_raw_unlock	211.785s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4513.560s	17852.425us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4546.520s	19460.988us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	798.770s	6013.703us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	798.770s	6013.703us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	798.770s	6013.703us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	353.120s	3373.426us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1407.570s	22160.584us	1	1	100.00
	chip_sw_otbn_mem_scramble	353.120s	3373.426us	1	1	100.00
	chip_sw_keymgr_key_derivation	1747.520s	9551.970us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	526.180s	5620.899us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	226.390s	2994.958us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1407.570s	22160.584us	1	1	100.00
	chip_sw_otbn_mem_scramble	353.120s	3373.426us	1	1	100.00
	chip_sw_keymgr_key_derivation	1747.520s	9551.970us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	526.180s	5620.899us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	226.390s	2994.958us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	433.540s	4483.499us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	163.310s	2475.028us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	249.220s	2745.583us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	584.330s	7228.393us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	628.600s	5465.167us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	689.260s	7046.938us	0	1	0.00
	chip_sw_lc_ctrl_transition	441.200s	6181.007us	1	1	100.00
	chip_prim_tl_access	254.270s	10978.333us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	254.270s	10978.333us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	1146.810s	7885.536us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	107.600s	2893.942us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1222.660s	27983.910us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	345.190s	6926.633us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	459.810s	7174.075us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	509.350s	6863.083us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1360.170s	22437.116us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1161.090s	14153.689us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	518.760s	8020.444us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	1332.850s	12571.919us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	554.160s	5691.486us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	107.600s	2893.942us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	434.470s	5635.929us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	3076.590s	33708.150us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	334.420s	6152.526us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	214.480s	3404.137us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	263.560s	6051.883us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	741.140s	7211.676us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1086.260s	9742.182us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2079.870s	29520.944us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	203.790s	2902.246us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	474.000s	4947.788us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	440.630s	10464.750us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	440.630s	10464.750us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1086.260s	9742.182us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	263.560s	6051.883us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	554.160s	5691.486us	1	1	100.00
	chip_sw_pwrmgr_smoketest	495.640s	6150.278us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	470.280s	5475.823us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	592.330s	5263.644us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	340.000s	4547.091us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1363.890s	12442.448us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	234.470s	3484.318us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	474.000s	4947.788us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	817.380s	6481.461us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	663.550s	5063.169us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	545.850s	5056.596us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	234.710s	3259.657us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	226.390s	2994.958us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	592.330s	5263.644us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	592.330s	5263.644us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	815.180s	10515.262us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1446.770s	13315.600us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	470.280s	5475.823us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	304.420s	3776.957us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	476.790s	6779.451us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	364.980s	5443.426us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	44.560s	2098.324us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	706.050s	5296.375us	1	1	100.00
	chip_plic_all_irqs_10	390.000s	3387.470us	1	1	100.00
	chip_plic_all_irqs_20	489.410s	4806.815us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	238.960s	2644.676us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	254.820s	2956.617us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3933.130s	15537.582us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	554.170s	7159.199us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	269.090s	3720.782us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	291.390s	3930.451us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	254.090s	2985.149us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	526.180s	5620.899us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	472.590s	5099.845us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	620.530s	7454.331us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	460.670s	9302.193us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	774.560s	8964.534us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	474.000s	4947.788us	1	1	100.00
	chip_sw_data_integrity_escalation	564.690s	5647.990us	1	1	100.00
chip_sw_sysrst_ctrl_reset				1	2	50.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	741.140s	7211.676us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1053.480s	23387.988us	0	1	0.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	214.150s	3379.775us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	342.650s	3620.617us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	440.740s	4198.703us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				0	1	0.00
	chip_sw_sysrst_ctrl_reset	1053.480s	23387.988us	0	1	0.00
chip_sw_sysrst_ctrl_sleep_reset				0	1	0.00
	chip_sw_sysrst_ctrl_reset	1053.480s	23387.988us	0	1	0.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3013.500s	21122.968us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3013.500s	21122.968us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	515.900s	5693.043us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.165s	0.000us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	233.740s	3261.924us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	203.540s	3404.214us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	316.180s	3326.611us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	402.290s	4085.241us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1055.170s	8448.823us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5590.560s	31883.596us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2183.980s	11850.033us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	212.290s	2842.987us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	217.700s	2911.344us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	141.430s	2580.540us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9930.260s	71569.714us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1392.220s	6347.543us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	597.100s	7756.909us	0	1	0.00
	rom_e2e_jtag_debug_dev	184.380s	4425.698us	0	1	0.00
	rom_e2e_jtag_debug_rma	264.090s	3861.710us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	93.309s	0.000us	0	1	0.00
	rom_e2e_jtag_inject_dev	159.369s	0.000us	0	1	0.00
	rom_e2e_jtag_inject_rma	39.878s	0.000us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	188.233s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	329.300s	3774.225us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	520.860s	3135.001us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	1154.910s	5763.044us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1282.430s	8057.832us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	314.760s	2490.621us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	759.180s	5751.921us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	218.540s	2840.959us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	259.790s	3053.212us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	418.990s	6207.603us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	377.170s	5018.763us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1086.260s	9742.182us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	597.100s	7756.909us	0	1	0.00
	rom_e2e_jtag_debug_dev	184.380s	4425.698us	0	1	0.00
	rom_e2e_jtag_debug_rma	264.090s	3861.710us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	501.650s	5672.806us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	474.000s	4947.788us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6379.550s	38105.106us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6379.550s	38105.106us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	234.900s	3857.191us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	486.150s	4148.394us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	4040.120s	18949.440us	1	1	100.00

unmapped

8/11 passed

72.73 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	11	72.73
	chip_sival_flash_info_access	265.550s	2983.044us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	432.800s	5137.970us	1	1	100.00
	chip_sw_otp_ctrl_rot_auth_config	5.180s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	202.300s	2660.483us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	257.130s	4043.702us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	248.900s	3641.460us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	11.622s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	225.060s	2988.659us	1	1	100.00
	ate_bootstrap_flash_erase	743.940s	10010.200us	0	1	0.00
	ate_bootstrap_one_frame	6951.740s	45219.278us	1	1	100.00
	ate_bootstrap_disjoint	10052.650s	85012.042us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				42 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	39850646763553621603001452457113785861719601339338704515294814348261711401909	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	114549745792141879745654557712700584475207594864558402766958363368636581055450	None	---- STDERR ---- Another command (pid=381477) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	98986708148484161438896391145224222509757644950939822514330291382246825897938	None	Another command (pid=927050) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=940642) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=874386) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	11485876921720516531978080147776393204670371026108380141716325098622715574378	None	Another command (pid=460741) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=448340) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=624958) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	93470673119943429162452805567141736650331386798500105164352807704462003392541	None	---- STDERR ---- Another command (pid=481359) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=551072) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	14412349894187515026924830134946342611221264237153836763441699327773046205166	None	Another command (pid=481359) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=551072) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=508051) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	96892381787065330161904967696631721002329032221767749430930735944319760735132	None	Another command (pid=650225) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=675375) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=651137) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	64231967860356123392115807190394296524151067684800543127681654151996565463514	None	Another command (pid=624958) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=497509) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=491043) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	47555656403076028706008523314170613557049924301350775871525421699010670417302	None	Another command (pid=681327) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=638344) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=642934) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	8894520432990739787073937623980264460879404716440799396703401522413590817074	None	Another command (pid=650225) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=663487) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=651137) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	44420095051823672262065151621231041164225363156998909543187502512765423975297	None	Another command (pid=460741) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=540059) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=608038) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	49922728787821125198775766305561632792905357179569171279539480323056540247673	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	106933966963502275813515290117644797912972734469531640773667966945858821248383	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	71318864420683175065491736314328089367247098613461906622087631064368878876986	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26388843562159066760824769738600459080642076358090831153056908014662090612444	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	111522187842978935260219898701026506464575257113152534328644558347407883223272	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	64704081960912003933894670978314558530026944387939397582596867335369594211412	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_bad_dev	25006190472996964793282139513236192244505049261592645669140969362820000106134	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_bad_prod	608116422137613849663812795346494452299479460038357186009698354466727564158	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	22352854459605093831017773434756802655613358699402282393338343411400834169129	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6699844274574764287672294859888258897350510999552741271093837784061693661571	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	109223211264991564229726267464747260442559487191314596612083567452584972091275	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	17120115585130866432948212899839452115701996392351693367974284265554970745659	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	109113729060340798935403228803489335838199968234071039168008131690974907060519	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	44026951109283663367240692950162619564990195220013731998242437491068090880765	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	108195026699997378427818948640131888333258244829931385120922290636739589367382	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	1283521344128318080485357938390970031065112281090426521669255668318557918106	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	62236020649888941135730012284774449084958340292132931778726359413167031638401	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	23284936330601397055513063457455109106407503012943413975284886450553584358550	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	47807016886492655627421622561552464070652851377368148952787100258482560060930	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	101828339528583645266033816222940252830186507249331114682915157076255263092636	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	18358201354604029119790501971068299118311808364364665297618751263400174734933	None	Another command (pid=454182) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=491303) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=527988) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	87729233897078970164983482671032516775670987404796088193299815121935439948220	None	---- STDERR ---- Another command (pid=381477) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	20462636360208561483240952688490764867934528894199173278503924626237959811892	None	Another command (pid=460741) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=540059) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=624958) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	61183777639672833103691287602355024132825700948635831311530379393062798453266	None	Another command (pid=590839) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=623429) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=460741) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	29494263444719527864729753677909725264130190221059264973417571992262405261237	None	Another command (pid=698793) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=652817) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=701333) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_jtag_inject_test_unlocked0	4159264517003055629415332101781462434855730317518704378454261931796711365931	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_jtag_inject_dev	87231136568736504360581075223771554495460246695021042464885622703778707996204	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_jtag_inject_rma	34757076748496223997976684494355749394707957688582851988092520965332096065927	None	File "/nightly/current_run/opentitan/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl fail("Bitstream cache not initialized properly.") Error in fail: Bitstream cache not initialized properly. ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly. ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	89911222807534530646842849128912927977407139223288901639079370405093915228996	None	Another command (pid=698793) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=652817) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=701333) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	100517960581341501085731473591891261926697285673478466512082623018358205635373	None	Another command (pid=462728) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=454510) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=463024) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	52584038571191134692915016647601319206708123806182709393454169694193606565170	None	Another command (pid=491043) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=473271) is running. Waiting for it to complete on the server (server_pid=277761)... Another command (pid=581355) is running. Waiting for it to complete on the server (server_pid=277761)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Offending '(rstreqs[*] && (reset_cause == HwReq))'				4 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	62706331151007772555425843087109205547268289787302694781067323810567015199068	315	UVM_ERROR @ 6051.883500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 6051.883500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	52992097505913912400623160135361600641070729951073685132125816834295201587341	325	UVM_ERROR @ 7174.075000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7174.075000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sysrst_ctrl_reset	74682282619521814331939510983738807083400925329303697183513171035808063394873	334	UVM_ERROR @ 23387.988000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 23387.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	98879740792861337955873794337693854396132938566172093658085863587891371595138	319	UVM_ERROR @ 8020.444000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8020.444000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				4 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	99728682630146225127062015110008617887334222939719669717121159808136335375725	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	56964551818163637647409519171916600955165689764426527590770151662843296128340	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	62291758994036051702910711563189652646729314318327141177220145798905589415101	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	89902651240452912786280027717224273866684704461935029440725978244803605597170	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	939083025894783166538930315001389949327398448136647443418218137316466375978	369	UVM_INFO @ 10465.569058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	29348358234967045948893958741182016657455852949718114693431893018564967772295	369	UVM_INFO @ 10880.201500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	77160354107195771007868119535415274712461549176663589599012171091106981597585	341	UVM_INFO @ 7511.024859 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	94688077325590960213804368400204103966605709732837534253097449501777216704209	316	UVM_ERROR @ 3053.211576 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3053.211576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	13981102519996861745721871186032158900317726316970936816901422856573756483555	312	UVM_ERROR @ 3634.317804 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3634.317804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	66084326451790437017066681528759778149016114754129716171155950050762445788953	None
	chip_sw_alert_handler_lpg_sleep_mode_pings	66016172184886156458153863185810577284897069989505100752492681585066994969935	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				2 test runs
	chip_tl_errors	73440528925880060882822268269740316453590734512847184653503183026344882335704	217	TL item was: req: (cip_tl_seq_item@32622) { a_addr: 'h105f0 a_data: 'hf4fa94fd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1b6b3 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2156.839575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_csr_mem_rw_with_rand_reset	2872597919410779629486231522296714597813154564904282956657545121163016448066	224	TL item was: req: (cip_tl_seq_item@31680) { a_addr: 'h10764 a_data: 'h8bc491cd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h1a57b d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2316.564762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	84151526507618362205662613064361231411545787496591796034065389072387836704309	320	UVM_INFO @ 3720.781720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	82939854763972593306668863265671132446554572581479407637730396882495367672632	309	UVM_INFO @ 2611.654188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	44535913445820090210476048042680236063997495488444904281293844630522793586435	342	UVM_INFO @ 7046.938184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	68156725337108042922250118527110726535775727308723401825028722272860097769557	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	103932050457158459785236916412057412845745580711808712990902794658759561738589	303	UVM_ERROR @ 2893.941640 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2893.941640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	97029559289212231944076506066312705721649474547319587793417450583389532175516	313	UVM_ERROR @ 3404.136572 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3404.136572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	46365395936575588104333561743524748685788475972611000847925542569218312574664	307	UVM_INFO @ 3061.500696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	77936635049527198478729160081327094422602600868919668383040251208212785083533	308	UVM_INFO @ 2895.961042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	100542024345968447618944418864317531602134508440819193851212940695532191168300	343	UVM_INFO @ 3774.225149 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	52678539083665002162930019243822547013704990250640316400984490994827616490867	215	UVM_INFO @ 2098.323750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	48785232970286798701786510008321285120864981306769583853899412540543812267409	312	UVM_INFO @ 3930.549500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	73557272956040160821503546825274329375327166008972088151904601267097463094993	318	UVM_INFO @ 2503.430000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	3767156485906627849039722582744687526171345575546934544906286721989813366428	327	UVM_INFO @ 10032.374454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	36255460239104829825583380839515133663568845822178145197060049918068552718248	272	UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_meas	103819714055598801221002415447135416023424963867567959106625510429965770234877	319	UVM_INFO @ 15465.905620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_invalid_meas	85781451022077920653204775780724246312653816700909277137368989851011566936360	319	UVM_INFO @ 17420.493010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	50810130915590325904145837890484105803947402724335475361153316702890808615668	327	UVM_ERROR @ 5809.165996 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 5809.165996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---