Simulation Results: clkmgr

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.20 %
  • code
  • 98.25 %
  • assert
  • 95.76 %
  • func
  • 85.59 %
  • line
  • 98.95 %
  • branch
  • 98.48 %
  • cond
  • 94.61 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.360s 72.327us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.170s 25.063us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.890s 52.562us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.290s 327.299us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.880s 48.318us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.150s 37.441us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.890s 52.562us 1 1 100.00
clkmgr_csr_aliasing 1.880s 48.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.970s 34.224us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.060s 15.039us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.830s 23.806us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.080s 31.983us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.360s 72.327us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.670s 1767.478us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.700s 501.751us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.670s 1767.478us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 3.490s 587.638us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.600s 144.066us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.730s 342.707us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.730s 342.707us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.170s 25.063us 1 1 100.00
clkmgr_csr_rw 0.890s 52.562us 1 1 100.00
clkmgr_csr_aliasing 1.880s 48.318us 1 1 100.00
clkmgr_same_csr_outstanding 1.540s 57.098us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.170s 25.063us 1 1 100.00
clkmgr_csr_rw 0.890s 52.562us 1 1 100.00
clkmgr_csr_aliasing 1.880s 48.318us 1 1 100.00
clkmgr_same_csr_outstanding 1.540s 57.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.880s 1.650us 0 1 0.00
clkmgr_tl_intg_err 66.720s 10023.017us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.760s 125.831us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.760s 125.831us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.760s 125.831us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.760s 125.831us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.260s 179.786us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 66.720s 10023.017us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.670s 1767.478us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.700s 501.751us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.760s 125.831us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.230s 18.382us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.930s 16.309us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.020s 25.845us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.000s 20.988us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.370s 74.792us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.890s 52.562us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.880s 1.650us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 52.562us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 52.562us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.880s 1.650us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.070s 503.893us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 56.260s 5894.524us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 1 test run
clkmgr_sec_cm 110956396647465797044467838550457581892315930355678343655842381784947115445071 77
UVM_INFO @ 1649992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault 1 test run
clkmgr_tl_intg_err 27599044351121138647391416381689582102462759655475733805323375815389459700657 119
UVM_INFO @ 10023017425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---