Simulation Results: csrng

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.34 %
  • code
  • 92.31 %
  • assert
  • 93.23 %
  • func
  • 79.48 %
  • block
  • 96.98 %
  • line
  • 97.73 %
  • branch
  • 92.42 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 75.408us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 59.773us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 73.383us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 13.000s 497.944us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 6.000s 108.515us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 35.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 73.383us 1 1 100.00
csrng_csr_aliasing 6.000s 108.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 470.030us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 7.000s 263.470us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 7.000s 263.470us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 529.000s 33764.046us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 22.409us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 21.655us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 80.440us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 80.440us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 59.773us 1 1 100.00
csrng_csr_rw 3.000s 73.383us 1 1 100.00
csrng_csr_aliasing 6.000s 108.515us 1 1 100.00
csrng_same_csr_outstanding 8.000s 440.041us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 59.773us 1 1 100.00
csrng_csr_rw 3.000s 73.383us 1 1 100.00
csrng_csr_aliasing 6.000s 108.515us 1 1 100.00
csrng_same_csr_outstanding 8.000s 440.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
csrng_tl_intg_err 3.000s 87.231us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 15.339us 1 1 100.00
csrng_csr_rw 3.000s 73.383us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 470.030us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 529.000s 33764.046us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 470.030us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 529.000s 33764.046us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 470.030us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 87.231us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
csrng_sec_cm 3.000s 137.928us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 20.000s 1713.245us 1 1 100.00
csrng_err 2.000s 25.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 12777942928338506483218478847809678942357695105728710853702509239655483113980 139
UVM_INFO @ 263470041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 77580240354343812357157259997577235216936628975506327460768009809470027804233 None