Simulation Results: edn/edn0

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.27 %
  • code
  • 79.80 %
  • assert
  • 95.01 %
  • func
  • 75.00 %
  • line
  • 97.17 %
  • branch
  • 90.10 %
  • cond
  • 82.99 %
  • toggle
  • 76.03 %
  • FSM
  • 52.69 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.970s 107.186us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.030s 33.103us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.210s 15.177us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.010s 138.278us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.310s 24.220us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.700s 23.595us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.210s 15.177us 1 1 100.00
edn_csr_aliasing 1.310s 24.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.710s 31.292us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.710s 31.292us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.710s 31.292us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.310s 26.641us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.260s 42.352us 1 1 100.00
errs 1 1 100.00
edn_err 1.260s 95.937us 1 1 100.00
disable 2 2 100.00
edn_disable 1.220s 30.537us 1 1 100.00
edn_disable_auto_req_mode 1.570s 31.089us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.760s 120.972us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.010s 39.345us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.020s 32.542us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.190s 73.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.190s 73.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.030s 33.103us 1 1 100.00
edn_csr_rw 1.210s 15.177us 1 1 100.00
edn_csr_aliasing 1.310s 24.220us 1 1 100.00
edn_same_csr_outstanding 1.050s 40.492us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.030s 33.103us 1 1 100.00
edn_csr_rw 1.210s 15.177us 1 1 100.00
edn_csr_aliasing 1.310s 24.220us 1 1 100.00
edn_same_csr_outstanding 1.050s 40.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 9.270s 4024.158us 1 1 100.00
edn_tl_intg_err 1.850s 195.277us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 42.783us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.260s 42.352us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.270s 4024.158us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.270s 4024.158us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 9.270s 4024.158us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 9.270s 4024.158us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.260s 42.352us 1 1 100.00
edn_sec_cm 9.270s 4024.158us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.260s 42.352us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.850s 195.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 12.910s 563.799us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 56932694351552180475892688901801840948024715791420474731945341626976836447222 150
UVM_INFO @ 563798695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---