Simulation Results: edn/edn1

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.78 %
  • code
  • 83.38 %
  • assert
  • 97.14 %
  • func
  • 79.83 %
  • line
  • 98.41 %
  • branch
  • 93.94 %
  • cond
  • 90.15 %
  • toggle
  • 87.80 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.110s 18.072us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.110s 16.489us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.100s 12.532us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.500s 517.983us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.400s 142.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 55.861us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.100s 12.532us 1 1 100.00
edn_csr_aliasing 1.400s 142.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.710s 101.819us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.710s 101.819us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.710s 101.819us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.040s 28.432us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 50.871us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 36.936us 1 1 100.00
disable 2 2 100.00
edn_disable 1.130s 12.689us 1 1 100.00
edn_disable_auto_req_mode 1.430s 52.107us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.530s 257.379us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.010s 12.952us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.110s 63.609us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.240s 162.925us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.240s 162.925us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.110s 16.489us 1 1 100.00
edn_csr_rw 1.100s 12.532us 1 1 100.00
edn_csr_aliasing 1.400s 142.084us 1 1 100.00
edn_same_csr_outstanding 1.180s 391.854us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.110s 16.489us 1 1 100.00
edn_csr_rw 1.100s 12.532us 1 1 100.00
edn_csr_aliasing 1.400s 142.084us 1 1 100.00
edn_same_csr_outstanding 1.180s 391.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.650s 1199.221us 1 1 100.00
edn_tl_intg_err 2.190s 118.877us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.240s 18.162us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 50.871us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.650s 1199.221us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.650s 1199.221us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.650s 1199.221us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.650s 1199.221us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 50.871us 1 1 100.00
edn_sec_cm 4.650s 1199.221us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 50.871us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.190s 118.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 21.040s 16770.433us 1 1 100.00