Simulation Results: flash_ctrl

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.65 %
  • code
  • 94.16 %
  • assert
  • 96.76 %
  • func
  • 96.04 %
  • line
  • 95.93 %
  • branch
  • 97.14 %
  • cond
  • 93.84 %
  • toggle
  • 98.16 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 55.550s 23.190us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.550s 30.629us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.920s 667.886us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.230s 186.019us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 40.600s 1250.773us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 26.190s 229.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 15.910s 600.157us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.230s 186.019us 1 1 100.00
flash_ctrl_csr_aliasing 26.190s 229.393us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 10.500s 60.402us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 9.600s 17.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.850s 22.888us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 11.870s 248.617us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1642.510s 338490.662us 1 1 100.00
flash_ctrl_hw_rma_reset 612.710s 160207.713us 1 1 100.00
flash_ctrl_lcmgr_intg 11.220s 72.592us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1716.680s 222502.435us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 267.660s 5890.589us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.990s 20.201us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1913.590s 89976.704us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 89.320s 2924.273us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 21.850s 58.239us 1 1 100.00
flash_ctrl_rw_evict_all_en 24.380s 108.073us 1 1 100.00
flash_ctrl_re_evict 18.310s 63.221us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 195.760s 4565.090us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 195.760s 4565.090us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 112.030s 14990.427us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.750s 376.884us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 121.960s 101.835us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 470.700s 16128.215us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 324.450s 2691.068us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 999.350s 494.544us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.650s 22.678us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 144.460s 1177.891us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 17.070s 97.172us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.670s 27.372us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 572.900s 896.180us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 67.850s 5821.743us 1 1 100.00
flash_ctrl_otp_reset 69.990s 42.831us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1642.510s 338490.662us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 101.080s 5580.362us 1 1 100.00
flash_ctrl_intr_wr 58.900s 13877.738us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 210.700s 43686.454us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 141.300s 21296.781us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 45.810s 4001.855us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 45.480s 3425.673us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 19.860s 132.985us 1 1 100.00
flash_ctrl_ro_derr 98.100s 5173.847us 1 1 100.00
flash_ctrl_rw_derr 161.750s 3374.689us 1 1 100.00
flash_ctrl_derr_detect 133.030s 1558.728us 1 1 100.00
flash_ctrl_integrity 531.140s 21991.409us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 19.140s 25.459us 1 1 100.00
flash_ctrl_ro_serr 117.660s 731.679us 1 1 100.00
flash_ctrl_rw_serr 183.910s 3805.412us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 44.310s 375.248us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 66.980s 3552.027us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 147.270s 2476.730us 1 1 100.00
flash_ctrl_write_word_sweep 11.330s 41.409us 1 1 100.00
flash_ctrl_read_word_sweep 10.670s 26.447us 1 1 100.00
flash_ctrl_ro 92.220s 2507.766us 1 1 100.00
flash_ctrl_rw 411.860s 16757.198us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 30.270s 506.756us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 628.100s 42158.447us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 114.600s 10020.533us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 11.620s 57.081us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 11.020s 29.892us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 12.000s 60.903us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 12.000s 60.903us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.920s 667.886us 1 1 100.00
flash_ctrl_csr_rw 8.230s 186.019us 1 1 100.00
flash_ctrl_csr_aliasing 26.190s 229.393us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.150s 131.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.920s 667.886us 1 1 100.00
flash_ctrl_csr_rw 8.230s 186.019us 1 1 100.00
flash_ctrl_csr_aliasing 26.190s 229.393us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.150s 131.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 47.730s 107.413us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 47.730s 107.413us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 47.730s 107.413us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 47.730s 107.413us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 28.760s 621.580us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
flash_ctrl_tl_intg_err 377.120s 729.141us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 377.120s 729.141us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 377.120s 729.141us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 24.300s 145.912us 1 1 100.00
flash_ctrl_wr_intg 13.040s 47.883us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 55.550s 23.190us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 69.990s 42.831us 1 1 100.00
flash_ctrl_disable 17.070s 97.172us 1 1 100.00
flash_ctrl_sec_info_access 57.800s 2235.690us 1 1 100.00
flash_ctrl_connect 8.670s 27.372us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.390s 72.793us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.230s 186.019us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 47.730s 107.413us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.230s 186.019us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 47.730s 107.413us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.230s 186.019us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 47.730s 107.413us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 17.070s 97.172us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 24.300s 145.912us 1 1 100.00
flash_ctrl_access_after_disable 6.910s 20.422us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.430s 62.900us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 17.070s 97.172us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.750s 376.884us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 411.860s 16757.198us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 183.910s 3805.412us 1 1 100.00
flash_ctrl_rw_derr 161.750s 3374.689us 1 1 100.00
flash_ctrl_integrity 531.140s 21991.409us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1642.510s 338490.662us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 23.520s 743.314us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 11.510s 49.367us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 13.860s 157.756us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1872.340s 1932.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 22.480s 92.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 122.590s 769.204us 1 1 100.00