Simulation Results: hmac

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.07 %
  • code
  • 97.31 %
  • assert
  • 96.70 %
  • func
  • 43.21 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 96.40 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.210s 614.484us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.070s 85.599us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.330s 33.507us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.380s 359.926us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 9.530s 464.764us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.040s 51.713us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.330s 33.507us 1 1 100.00
hmac_csr_aliasing 9.530s 464.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 20.370s 1306.474us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 36.760s 601.080us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 12.980s 158.189us 1 1 100.00
hmac_test_sha384_vectors 473.870s 10152.302us 1 1 100.00
hmac_test_sha512_vectors 25.780s 250.127us 1 1 100.00
hmac_test_hmac256_vectors 13.690s 293.837us 1 1 100.00
hmac_test_hmac384_vectors 10.690s 310.231us 1 1 100.00
hmac_test_hmac512_vectors 13.700s 297.082us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.110s 282.722us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 592.490s 3261.462us 1 1 100.00
error 1 1 100.00
hmac_error 5.240s 370.735us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 154.770s 44491.458us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.210s 614.484us 1 1 100.00
hmac_long_msg 20.370s 1306.474us 1 1 100.00
hmac_back_pressure 36.760s 601.080us 1 1 100.00
hmac_datapath_stress 592.490s 3261.462us 1 1 100.00
hmac_burst_wr 5.110s 282.722us 1 1 100.00
hmac_stress_all 47.730s 8732.651us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.210s 614.484us 1 1 100.00
hmac_long_msg 20.370s 1306.474us 1 1 100.00
hmac_back_pressure 36.760s 601.080us 1 1 100.00
hmac_datapath_stress 592.490s 3261.462us 1 1 100.00
hmac_wipe_secret 154.770s 44491.458us 1 1 100.00
hmac_test_sha256_vectors 12.980s 158.189us 1 1 100.00
hmac_test_sha384_vectors 473.870s 10152.302us 1 1 100.00
hmac_test_sha512_vectors 25.780s 250.127us 1 1 100.00
hmac_test_hmac256_vectors 13.690s 293.837us 1 1 100.00
hmac_test_hmac384_vectors 10.690s 310.231us 1 1 100.00
hmac_test_hmac512_vectors 13.700s 297.082us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.210s 614.484us 1 1 100.00
hmac_long_msg 20.370s 1306.474us 1 1 100.00
hmac_back_pressure 36.760s 601.080us 1 1 100.00
hmac_datapath_stress 592.490s 3261.462us 1 1 100.00
hmac_burst_wr 5.110s 282.722us 1 1 100.00
hmac_error 5.240s 370.735us 1 1 100.00
hmac_wipe_secret 154.770s 44491.458us 1 1 100.00
hmac_test_sha256_vectors 12.980s 158.189us 1 1 100.00
hmac_test_sha384_vectors 473.870s 10152.302us 1 1 100.00
hmac_test_sha512_vectors 25.780s 250.127us 1 1 100.00
hmac_test_hmac256_vectors 13.690s 293.837us 1 1 100.00
hmac_test_hmac384_vectors 10.690s 310.231us 1 1 100.00
hmac_test_hmac512_vectors 13.700s 297.082us 1 1 100.00
hmac_stress_all 47.730s 8732.651us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 47.730s 8732.651us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.870s 80.439us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.900s 71.819us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.060s 676.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.060s 676.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.070s 85.599us 1 1 100.00
hmac_csr_rw 1.330s 33.507us 1 1 100.00
hmac_csr_aliasing 9.530s 464.764us 1 1 100.00
hmac_same_csr_outstanding 2.070s 45.123us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.070s 85.599us 1 1 100.00
hmac_csr_rw 1.330s 33.507us 1 1 100.00
hmac_csr_aliasing 9.530s 464.764us 1 1 100.00
hmac_same_csr_outstanding 2.070s 45.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.450s 95.476us 1 1 100.00
hmac_tl_intg_err 3.330s 194.133us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.330s 194.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.210s 614.484us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.520s 1652.391us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 153.630s 5423.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.170s 38.957us 1 1 100.00