Simulation Results

Simulation Results: i2c

20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
86.06 %

code
81.02 %

assert
95.77 %

func
81.40 %

line
96.29 %

branch
91.91 %

cond
84.59 %

toggle
89.45 %

FSM
42.86 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	52.700s	10637.026us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	11.360s	898.020us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.980s	63.104us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	35.267us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.430s	369.167us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.250s	938.555us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.290s	149.391us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	35.267us	1	1	100.00
	i2c_csr_aliasing	2.250s	938.555us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.220s	130.043us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	387.370s	89086.194us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	31.250s	2915.626us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.020s	91.092us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	75.640s	28478.118us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	32.160s	1517.606us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.280s	93.509us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.800s	664.580us	1	1	100.00
	i2c_host_fifo_reset_rx	14.220s	249.932us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	71.870s	3184.447us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	20.630s	1504.447us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.090s	53.135us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.680s	2208.507us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	50.950s	47812.560us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.830s	3089.505us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	6.700s	1293.655us	1	1	100.00
	i2c_target_intr_smoke	4.510s	686.463us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.850s	230.563us	1	1	100.00
	i2c_target_fifo_reset_tx	1.520s	175.126us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	72.620s	25439.006us	1	1	100.00
	i2c_target_stress_rd	6.700s	1293.655us	1	1	100.00
	i2c_target_intr_stress_wr	53.280s	26713.481us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.610s	5228.027us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	4.920s	781.462us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.350s	747.054us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	40.100s	10005.442us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.430s	2147.461us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.640s	306.400us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	31.250s	2915.626us	1	1	100.00
	i2c_host_perf_precise	3.520s	249.063us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	20.630s	1504.447us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.800s	133.137us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	3.980s	463.398us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.360s	1006.184us	1	1	100.00
	i2c_target_nack_txstretch	1.850s	735.895us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.180s	725.850us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.080s	508.510us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.990s	32.646us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	26.890us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.340s	169.015us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.340s	169.015us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.980s	63.104us	1	1	100.00
	i2c_csr_rw	1.000s	35.267us	1	1	100.00
	i2c_csr_aliasing	2.250s	938.555us	1	1	100.00
	i2c_same_csr_outstanding	1.490s	102.020us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.980s	63.104us	1	1	100.00
	i2c_csr_rw	1.000s	35.267us	1	1	100.00
	i2c_csr_aliasing	2.250s	938.555us	1	1	100.00
	i2c_same_csr_outstanding	1.490s	102.020us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.610s	535.151us	1	1	100.00
	i2c_sec_cm	1.360s	78.708us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.610s	535.151us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.490s	211.754us	1
target_error_intr				1
	i2c_target_unexp_stop	1.560s	511.806us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.930s	718.894us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				4 test runs
	i2c_host_error_intr	68946426578767937310871157584282039267026773467433393071465774895476756507234	96	UVM_INFO @ 130043031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	43051093697852046336034328002366558004050457754608623859948983262402316257404	161	UVM_INFO @ 89086194373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	6855929963265195849285542964430126478044849452640906015282978304412466965584	90	UVM_INFO @ 718894281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	85344890064640220090735540705174582555960207869584763052002324647705309305282	81	UVM_INFO @ 53135241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	17385247626445674712514570959723359133050039487999132257685188430962309899584	84	UVM_INFO @ 2208506791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	27339816237253231467950030888293896714189383245440845661485474302132844437753	78	UVM_INFO @ 511806352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	3592774819437188461647650882453509565870877318841147043844922012181704111196	79	UVM_INFO @ 10005442483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	22032061179408198642569268222935989238625652750783213405467468438459317885517	84	UVM_INFO @ 211753695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	13993977489579263672755335555917975560677653350023745945326394567030965162191	78	UVM_INFO @ 735895429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---