Simulation Results: kmac/masked

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.09 %
  • code
  • 89.63 %
  • assert
  • 96.10 %
  • func
  • 90.54 %
  • line
  • 98.71 %
  • branch
  • 95.78 %
  • cond
  • 90.01 %
  • toggle
  • 99.57 %
  • FSM
  • 64.08 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 51.800s 5942.060us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.190s 15.963us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.420s 30.590us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 16.630s 1924.446us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 8.240s 2704.848us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 3.190s 70.888us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.420s 30.590us 1 1 100.00
kmac_csr_aliasing 8.240s 2704.848us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.050s 40.138us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.780s 97.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 209.130s 25803.607us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 809.090s 9351.110us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 38.960s 4658.602us 1 1 100.00
kmac_test_vectors_sha3_256 31.030s 12454.644us 1 1 100.00
kmac_test_vectors_sha3_384 1135.510s 77990.427us 1 1 100.00
kmac_test_vectors_sha3_512 22.060s 1734.402us 1 1 100.00
kmac_test_vectors_shake_128 133.380s 15067.636us 1 1 100.00
kmac_test_vectors_shake_256 2521.620s 181008.815us 1 1 100.00
kmac_test_vectors_kmac 3.470s 53.597us 1 1 100.00
kmac_test_vectors_kmac_xof 2.920s 682.019us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 74.660s 5289.202us 1 1 100.00
app 1 1 100.00
kmac_app 107.810s 2637.164us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 49.550s 969.382us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 44.550s 4842.953us 1 1 100.00
error 0 1 0.00
kmac_error 364.280s 200000.000us 0 1 0.00
key_error 1 1 100.00
kmac_key_error 7.070s 3033.763us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 6.090s 519.328us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 3.730s 152.044us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.710s 38.284us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 71.520s 6575.601us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.840s 70.256us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 646.930s 44843.834us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.110s 45.682us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.170s 45.810us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.490s 103.026us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.490s 103.026us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.190s 15.963us 1 1 100.00
kmac_csr_rw 1.420s 30.590us 1 1 100.00
kmac_csr_aliasing 8.240s 2704.848us 1 1 100.00
kmac_same_csr_outstanding 2.070s 103.007us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.190s 15.963us 1 1 100.00
kmac_csr_rw 1.420s 30.590us 1 1 100.00
kmac_csr_aliasing 8.240s 2704.848us 1 1 100.00
kmac_same_csr_outstanding 2.070s 103.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.350s 45.151us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.350s 45.151us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.350s 45.151us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.350s 45.151us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.990s 86.844us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 48.310s 4333.981us 1 1 100.00
kmac_tl_intg_err 2.500s 264.949us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.500s 264.949us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.840s 70.256us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 51.800s 5942.060us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 74.660s 5289.202us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.350s 45.151us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 48.310s 4333.981us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 48.310s 4333.981us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 48.310s 4333.981us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 51.800s 5942.060us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.840s 70.256us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 48.310s 4333.981us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 60.410s 12404.421us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 51.800s 5942.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 58.770s 9588.814us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
kmac_error 54530110715725806922240624005922091075106178004463039646847069916857532903713 236
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 71021034354365216593670826140741518431930706120945998637592016183150617934727 230
UVM_INFO @ 9588814065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---