Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.34 %
  • code
  • 83.66 %
  • assert
  • 94.13 %
  • func
  • 93.24 %
  • line
  • 97.19 %
  • branch
  • 93.70 %
  • cond
  • 79.66 %
  • toggle
  • 85.14 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.150s 94.136us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.420s 62.163us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.230s 34.721us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.300s 130.849us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.180s 95.466us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.590s 304.467us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.230s 34.721us 1 1 100.00
lc_ctrl_csr_aliasing 2.180s 95.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 8.170s 56.724us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.600s 355.961us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.340s 12.196us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.010s 18.355us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.540s 1821.799us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_prog_failure 2.010s 18.355us 1 1 100.00
lc_ctrl_errors 10.540s 1821.799us 1 1 100.00
lc_ctrl_security_escalation 9.730s 1219.948us 1 1 100.00
lc_ctrl_jtag_state_failure 18.570s 913.544us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.820s 293.725us 1 1 100.00
lc_ctrl_jtag_errors 41.490s 39457.101us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.430s 229.054us 1 1 100.00
lc_ctrl_jtag_state_post_trans 22.540s 755.834us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.820s 293.725us 1 1 100.00
lc_ctrl_jtag_errors 41.490s 39457.101us 1 1 100.00
lc_ctrl_jtag_access 9.540s 1819.932us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.540s 15703.906us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.490s 329.750us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.850s 196.354us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 25.310s 2257.694us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 31.600s 1321.091us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.990s 52.044us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.950s 513.152us 1 1 100.00
lc_ctrl_jtag_alert_test 1.550s 37.547us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.280s 815.991us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.360s 15.702us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 36.050s 15625.417us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.510s 17.089us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.850s 574.130us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.850s 574.130us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.420s 62.163us 1 1 100.00
lc_ctrl_csr_rw 1.230s 34.721us 1 1 100.00
lc_ctrl_csr_aliasing 2.180s 95.466us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 41.046us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.420s 62.163us 1 1 100.00
lc_ctrl_csr_rw 1.230s 34.721us 1 1 100.00
lc_ctrl_csr_aliasing 2.180s 95.466us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 41.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
lc_ctrl_tl_intg_err 3.010s 332.666us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.010s 332.666us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.600s 355.961us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.730s 401.146us 1 1 100.00
lc_ctrl_sec_cm 7.340s 2490.137us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.730s 1219.948us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 8.170s 56.724us 1 1 100.00
lc_ctrl_jtag_state_post_trans 22.540s 755.834us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.980s 467.111us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.980s 467.111us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 17.380s 1221.515us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.600s 654.531us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.600s 654.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 75.180s 13729.261us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 32870524475234875135859307973091241563050602540552073779322432879639605029379 15295
UVM_INFO @ 13729260661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---