Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.76 %
  • code
  • 84.38 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.17 %
  • branch
  • 93.66 %
  • cond
  • 79.42 %
  • toggle
  • 86.21 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.280s 18.762us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.120s 58.342us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.370s 24.692us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.790s 97.119us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.540s 17.924us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.850s 20.357us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.370s 24.692us 1 1 100.00
lc_ctrl_csr_aliasing 1.540s 17.924us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 8.830s 473.280us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.740s 458.948us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.970s 67.209us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 4.100s 759.803us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.330s 164.954us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_prog_failure 4.100s 759.803us 1 1 100.00
lc_ctrl_errors 7.330s 164.954us 1 1 100.00
lc_ctrl_security_escalation 8.900s 2096.829us 1 1 100.00
lc_ctrl_jtag_state_failure 36.450s 1367.823us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.630s 108.042us 1 1 100.00
lc_ctrl_jtag_errors 37.220s 6151.864us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.750s 490.303us 1 1 100.00
lc_ctrl_jtag_state_post_trans 26.170s 1694.100us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.630s 108.042us 1 1 100.00
lc_ctrl_jtag_errors 37.220s 6151.864us 1 1 100.00
lc_ctrl_jtag_access 16.080s 1477.730us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.880s 2016.966us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.500s 145.058us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.840s 210.071us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.710s 409.650us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.570s 492.084us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.810s 41.734us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.090s 51.579us 1 1 100.00
lc_ctrl_jtag_alert_test 1.160s 435.864us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.210s 207.027us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 110.107us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 52.880s 2503.217us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.360s 59.809us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.830s 164.384us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.830s 164.384us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.120s 58.342us 1 1 100.00
lc_ctrl_csr_rw 1.370s 24.692us 1 1 100.00
lc_ctrl_csr_aliasing 1.540s 17.924us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.900s 30.993us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.120s 58.342us 1 1 100.00
lc_ctrl_csr_rw 1.370s 24.692us 1 1 100.00
lc_ctrl_csr_aliasing 1.540s 17.924us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.900s 30.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
lc_ctrl_tl_intg_err 2.510s 406.792us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.510s 406.792us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.740s 458.948us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.340s 1221.676us 1 1 100.00
lc_ctrl_sec_cm 8.930s 118.454us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.900s 2096.829us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 8.830s 473.280us 1 1 100.00
lc_ctrl_jtag_state_post_trans 26.170s 1694.100us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.130s 748.514us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.130s 748.514us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.140s 1691.620us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 11.520s 382.999us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 11.520s 382.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 72.860s 2931.438us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 234192659526235123816010306072146855520130914875374501101052544938842182678 7709
UVM_INFO @ 2503216528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 63263964678883866878075876320935201413619896994716809060747605464129146771141 6222
UVM_INFO @ 2931437936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---