Simulation Results: otp_ctrl

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.88 %
  • code
  • 78.46 %
  • assert
  • 94.11 %
  • func
  • 73.06 %
  • line
  • 88.87 %
  • branch
  • 84.49 %
  • cond
  • 92.87 %
  • toggle
  • 81.96 %
  • FSM
  • 44.10 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.940s 105.338us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.780s 713.175us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.500s 131.128us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.620s 596.299us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.770s 454.153us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 126.004us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.000s 79.124us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.620s 596.299us 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 126.004us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.920s 42.209us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.420s 39.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 16.610s 532.232us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.160s 202.763us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 11.590s 2002.398us 1 1 100.00
otp_ctrl_check_fail 8.100s 1064.139us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.490s 432.159us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 21.560s 2247.093us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.520s 556.042us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 18.120s 2099.188us 1 1 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 8.440s 234.739us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 6.030s 486.551us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 12.410s 1245.073us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 43.780s 36070.934us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.070s 43.227us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.960s 119.872us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 7.060s 369.948us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 7.060s 369.948us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.500s 131.128us 1 1 100.00
otp_ctrl_csr_rw 2.620s 596.299us 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 126.004us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.610s 556.855us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.500s 131.128us 1 1 100.00
otp_ctrl_csr_rw 2.620s 596.299us 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 126.004us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.610s 556.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
otp_ctrl_tl_intg_err 9.860s 2664.816us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 9.860s 2664.816us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.780s 713.175us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.780s 713.175us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
otp_ctrl_macro_errs 6.030s 486.551us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
otp_ctrl_macro_errs 6.030s 486.551us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 13.550s 470.576us 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.160s 202.763us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 8.100s 1064.139us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 21.560s 2247.093us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 21.560s 2247.093us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 21.560s 2247.093us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 21.560s 2247.093us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 21.560s 2247.093us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.780s 713.175us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 21.560s 2247.093us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.780s 713.175us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 158.350s 38924.437us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.490s 432.159us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.780s 713.175us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.780s 713.175us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 6.030s 486.551us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 26.200s 6983.832us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 85.330s 9725.795us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 3977402140200772024093933360648556974743772896073100619031241475404964593383 4776
UVM_INFO @ 1064139274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 58523828758772675104874157132860071372247903786119970809875886045243692606861 4394
UVM_INFO @ 486551241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---