Simulation Results: pattgen

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 79.942us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 17.808us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 13.597us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 4.000s 561.438us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 114.540us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 30.473us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 13.597us 1 1 100.00
pattgen_csr_aliasing 2.000s 114.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 11.000s 5690.675us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 12.000s 1340.737us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 79.732us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 146.000s 49767.633us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 12.804us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 12.490us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 112.956us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 112.956us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 17.808us 1 1 100.00
pattgen_csr_rw 1.000s 13.597us 1 1 100.00
pattgen_csr_aliasing 2.000s 114.540us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 14.957us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 17.808us 1 1 100.00
pattgen_csr_rw 1.000s 13.597us 1 1 100.00
pattgen_csr_aliasing 2.000s 114.540us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 14.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 191.594us 1 1 100.00
pattgen_sec_cm 1.000s 65.106us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 191.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 35.000s 3305.271us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 58.000s 10021.265us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) 1 test run
pattgen_inactive_level 7330307484355625791388831344823325903105294924137388667202106567515596326418 99
UVM_INFO @ 10021265122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 58387881928799783219403196102043509702835180474411409054577445321607932261289 158
UVM_ERROR @ 1563806824 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1563806824 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1563849376 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] 1 test run
pattgen_stress_all 72341867156120565483925565652297081229921034360898001001565402034385043553634 118
--> channel 0 item mismatch!
--> EXP:
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Name Type Size Value