| V1 |
|
100.00% |
| V2 |
|
90.91% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| pwm_smoke | 3.000s | 2553.928us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwm_csr_hw_reset | 2.000s | 28.852us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| pwm_csr_rw | 1.000s | 58.958us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwm_csr_bit_bash | 9.000s | 472.314us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwm_csr_aliasing | 2.000s | 34.290us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| pwm_csr_mem_rw_with_rand_reset | 2.000s | 34.097us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| pwm_csr_rw | 1.000s | 58.958us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 34.290us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dutycycle | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| pulse | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| blink | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| heartbeat | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| resolution | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| multi_channel | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| polarity | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| phase | 2 | 2 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| pwm_phase | 35.000s | 16668.842us | 1 | 1 | 100.00 | |
| lowpower | 1 | 1 | 100.00 | |||
| pwm_rand_output | 45.000s | 30043.906us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| pwm_perf | 31.000s | 14986.483us | 1 | 1 | 100.00 | |
| regwen | 0 | 1 | 0.00 | |||
| pwm_regwen | 189.000s | 12345.583us | 0 | 1 | 0.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| pwm_stress_all | 96.000s | 107239.387us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| pwm_alert_test | 2.000s | 30.098us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 3.000s | 141.566us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 3.000s | 141.566us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 2.000s | 28.852us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 1.000s | 58.958us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 34.290us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 1.000s | 42.132us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 2.000s | 28.852us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 1.000s | 58.958us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 34.290us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 1.000s | 42.132us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| pwm_tl_intg_err | 2.000s | 74.145us | 1 | 1 | 100.00 | |
| pwm_sec_cm | 1.000s | 46.924us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| pwm_tl_intg_err | 2.000s | 74.145us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| heartbeat_wrap | 1 | 1 | 100.00 | |||
| pwm_heartbeat_wrap | 34.000s | 17505.206us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (pwm_scoreboard.sv:386) scoreboard [scoreboard] | 1 test run | |||
| pwm_regwen | 18567473900628700769106804681884354761752740443810838208601469665934508080338 | 95 |
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 12345583081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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