Simulation Results: pwrmgr

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.90 %
  • code
  • 94.43 %
  • assert
  • 96.08 %
  • func
  • 97.20 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 93.78 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.970s 49.087us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.990s 113.188us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.920s 27.792us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.780s 2705.575us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.230s 43.217us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.140s 45.018us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.920s 27.792us 1 1 100.00
pwrmgr_csr_aliasing 1.230s 43.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.100s 34.253us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.100s 34.253us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.050s 30.820us 1 1 100.00
pwrmgr_lowpower_invalid 0.890s 70.441us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.970s 49.406us 1 1 100.00
pwrmgr_reset_invalid 1.170s 102.895us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.970s 49.406us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.120s 325.492us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.240s 190.354us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.850s 26.910us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.830s 1539.558us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.870s 32.093us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.190s 42.039us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.190s 42.039us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.990s 113.188us 1 1 100.00
pwrmgr_csr_rw 0.920s 27.792us 1 1 100.00
pwrmgr_csr_aliasing 1.230s 43.217us 1 1 100.00
pwrmgr_same_csr_outstanding 1.050s 286.961us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.990s 113.188us 1 1 100.00
pwrmgr_csr_rw 0.920s 27.792us 1 1 100.00
pwrmgr_csr_aliasing 1.230s 43.217us 1 1 100.00
pwrmgr_same_csr_outstanding 1.050s 286.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.860s 13.052us 0 1 0.00
pwrmgr_sec_cm 1.010s 27.904us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 1.010s 27.904us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 1.010s 27.904us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.860s 13.052us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.760s 754.992us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.120s 325.492us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.080s 48.372us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.800s 29.457us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 1.010s 27.904us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 1.010s 27.904us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 1.010s 27.904us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.770s 141.217us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.920s 32.302us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.960s 178.773us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.920s 27.792us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.920s 27.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 1.220s 124.471us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 10.900s 33231.581us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
pwrmgr_tl_intg_err 18310770390897711631958709605210472735973849717184606672669113744414010248359 78
UVM_INFO @ 13051997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 110557906300645041285770737008411102755646964279517315464440626100360535128978 86
UVM_INFO @ 27903876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 38138315681121273147892888440135156710961840628088728641687214712490865632299 79
UVM_ERROR @ 124470737 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 124470737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---