Simulation Results: rom_ctrl/32kb

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.84 %
  • code
  • 99.36 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.92 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.500s 137.484us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.660s 297.870us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.590s 164.318us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.200s 455.231us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.560s 164.256us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.280s 256.910us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.590s 164.318us 1 1 100.00
rom_ctrl_csr_aliasing 5.560s 164.256us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.260s 577.493us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.490s 164.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.720s 233.725us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.970s 455.664us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.460s 306.004us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.130s 815.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.780s 169.417us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.780s 169.417us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.660s 297.870us 1 1 100.00
rom_ctrl_csr_rw 4.590s 164.318us 1 1 100.00
rom_ctrl_csr_aliasing 5.560s 164.256us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.120s 538.164us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.660s 297.870us 1 1 100.00
rom_ctrl_csr_rw 4.590s 164.318us 1 1 100.00
rom_ctrl_csr_aliasing 5.560s 164.256us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.120s 538.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.750s 1856.500us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 227.690s 1923.852us 1 1 100.00
rom_ctrl_tl_intg_err 57.770s 1041.516us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 227.690s 1923.852us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 227.690s 1923.852us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 227.690s 1923.852us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 227.690s 1923.852us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.500s 137.484us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.500s 137.484us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.500s 137.484us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 57.770s 1041.516us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
rom_ctrl_kmac_err_chk 10.460s 306.004us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.320s 14703.348us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.750s 1856.500us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 227.690s 1923.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 47.610s 1627.051us 1 1 100.00