Simulation Results: rom_ctrl/64kb

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 96.82 %
  • assert
  • 96.66 %
  • func
  • 96.90 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.22 %
  • toggle
  • 100.00 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 12.020s 3849.490us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.960s 208.934us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.950s 390.918us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 9.540s 287.979us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.730s 1802.411us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.980s 552.362us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.950s 390.918us 1 1 100.00
rom_ctrl_csr_aliasing 8.730s 1802.411us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.350s 212.309us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 8.420s 1023.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 10.020s 536.090us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 31.560s 5301.731us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 16.580s 515.104us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 8.560s 747.006us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 12.880s 286.063us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 12.880s 286.063us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.960s 208.934us 1 1 100.00
rom_ctrl_csr_rw 7.950s 390.918us 1 1 100.00
rom_ctrl_csr_aliasing 8.730s 1802.411us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.310s 553.850us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.960s 208.934us 1 1 100.00
rom_ctrl_csr_rw 7.950s 390.918us 1 1 100.00
rom_ctrl_csr_aliasing 8.730s 1802.411us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.310s 553.850us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 59.390s 1565.826us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 466.530s 1253.798us 1 1 100.00
rom_ctrl_tl_intg_err 115.160s 526.354us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 466.530s 1253.798us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 466.530s 1253.798us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 466.530s 1253.798us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 466.530s 1253.798us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 12.020s 3849.490us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 12.020s 3849.490us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 12.020s 3849.490us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 115.160s 526.354us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
rom_ctrl_kmac_err_chk 16.580s 515.104us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.020s 5128.418us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 59.390s 1565.826us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 466.530s 1253.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 175.060s 4956.061us 1 1 100.00