Simulation Results: rstmgr

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.13 %
  • code
  • 99.26 %
  • assert
  • 97.86 %
  • func
  • 97.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.61 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.450s 111.898us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.130s 139.109us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.080s 64.240us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.120s 1166.757us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 3.130s 476.651us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.680s 188.781us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.080s 64.240us 1 1 100.00
rstmgr_csr_aliasing 3.130s 476.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.090s 133.372us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.830s 134.405us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.600s 257.612us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.180s 1681.331us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.180s 1681.331us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.180s 1681.331us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.180s 1681.331us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 20.110s 8006.419us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.020s 85.742us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 5.360s 709.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 5.360s 709.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.130s 139.109us 1 1 100.00
rstmgr_csr_rw 1.080s 64.240us 1 1 100.00
rstmgr_csr_aliasing 3.130s 476.651us 1 1 100.00
rstmgr_same_csr_outstanding 1.470s 146.248us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.130s 139.109us 1 1 100.00
rstmgr_csr_rw 1.080s 64.240us 1 1 100.00
rstmgr_csr_aliasing 3.130s 476.651us 1 1 100.00
rstmgr_same_csr_outstanding 1.470s 146.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 26.970s 16810.091us 1 1 100.00
rstmgr_tl_intg_err 2.500s 473.165us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 26.970s 16810.091us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 26.970s 16810.091us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.500s 473.165us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.340s 104.161us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.820s 1269.087us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.500s 302.283us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 26.970s 16810.091us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.080s 64.240us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.080s 64.240us 1 1 100.00