Simulation Results: rv_timer

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.41 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 89.41 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.040s 189.249us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.770s 54.275us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.860s 38.605us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.890s 1463.889us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.880s 30.908us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.910s 54.091us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.860s 38.605us 1 1 100.00
rv_timer_csr_aliasing 0.880s 30.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.190s 151.276us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.300s 2119.827us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 350.090s 283599.843us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 350.090s 283599.843us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.750s 5683.690us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.810s 82.842us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.850s 15.965us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.270s 146.649us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.270s 146.649us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 54.275us 1 1 100.00
rv_timer_csr_rw 0.860s 38.605us 1 1 100.00
rv_timer_csr_aliasing 0.880s 30.908us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 36.621us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.770s 54.275us 1 1 100.00
rv_timer_csr_rw 0.860s 38.605us 1 1 100.00
rv_timer_csr_aliasing 0.880s 30.908us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 36.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.080s 133.288us 1 1 100.00
rv_timer_tl_intg_err 1.650s 2083.030us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.650s 2083.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.220s 54.583us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.840s 82.463us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 15.510s 3033.610us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 52939611495141704916980491755674219173780127728048669451604028607864095167846 76
UVM_INFO @ 54582791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 73455076602003263510826906896810170712275097827109161385537043995560290083278 75
UVM_INFO @ 151276253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 83623357279705468207055708123958629907196637773204307280074481518692049336494 75
UVM_INFO @ 82463350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 82514497923855703938934842273616852010036743797365826937207924568299885923522 193
UVM_INFO @ 3033609703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---