Simulation Results: spi_device/1r1w

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.99 %
  • code
  • 93.09 %
  • assert
  • 94.64 %
  • func
  • 76.24 %
  • line
  • 98.88 %
  • branch
  • 98.27 %
  • cond
  • 95.38 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 69.580s 8734.289us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.190s 43.053us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.910s 251.200us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 20.570s 6239.293us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 7.190s 1282.968us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.900s 29.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.910s 251.200us 1 1 100.00
spi_device_csr_aliasing 7.190s 1282.968us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.960s 24.886us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.140s 153.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.080s 14.439us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.900s 1.629us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.020s 3.636us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 4.260s 134.790us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 4.260s 134.790us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.020s 36.560us 1 1 100.00
spi_device_tpm_sts_read 1.090s 17.386us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 17.830s 2810.053us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 17.800s 32033.595us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.970s 153.505us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.970s 153.505us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.780s 338.289us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.780s 338.289us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.780s 338.289us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.780s 338.289us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.780s 338.289us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.350s 373.969us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 2.370s 113.744us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 2.370s 113.744us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 2.370s 113.744us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 19.340s 3309.452us 1 1 100.00
spi_device_read_buffer_direct 4.950s 289.547us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 2.370s 113.744us 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 275.660s 105707.792us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.360s 239.951us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.360s 239.951us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 69.580s 8734.289us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 93.420s 13407.364us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 141.730s 76559.405us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.020s 35.050us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.070s 59.148us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.070s 358.642us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.070s 358.642us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.190s 43.053us 1 1 100.00
spi_device_csr_rw 1.910s 251.200us 1 1 100.00
spi_device_csr_aliasing 7.190s 1282.968us 1 1 100.00
spi_device_same_csr_outstanding 1.800s 107.630us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.190s 43.053us 1 1 100.00
spi_device_csr_rw 1.910s 251.200us 1 1 100.00
spi_device_csr_aliasing 7.190s 1282.968us 1 1 100.00
spi_device_same_csr_outstanding 1.800s 107.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.460s 63.405us 1 1 100.00
spi_device_tl_intg_err 10.960s 570.807us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.960s 570.807us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 109.450s 35306.387us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 106388174906836188326679911221627325117319484576196595801673151457887411649593 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1035484 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1035484 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[913])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 87759078203091969589536302758700781006882379464567215555536716403206193842550 76
UVM_ERROR @ 1078848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x78c2a1 [11110001100001010100001] vs 0x0 [0])
UVM_ERROR @ 1148848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfb96f6 [111110111001011011110110] vs 0x0 [0])
UVM_ERROR @ 1215848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaedb26 [101011101101101100100110] vs 0x0 [0])
UVM_ERROR @ 1271848 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4c7a34 [10011000111101000110100] vs 0x0 [0])