Simulation Results: spi_device/2p

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.54 %
  • code
  • 94.04 %
  • assert
  • 94.62 %
  • func
  • 73.96 %
  • line
  • 98.94 %
  • branch
  • 98.32 %
  • cond
  • 95.86 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 47.410s 3551.443us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.510s 167.433us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.450s 289.877us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 29.010s 7234.635us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.230s 1255.814us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.440s 88.524us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.450s 289.877us 1 1 100.00
spi_device_csr_aliasing 6.230s 1255.814us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.910s 18.643us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.440s 57.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.120s 14.094us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.440s 113.995us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.050s 50.703us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.140s 18.606us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.140s 18.606us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 12.720s 15923.825us 1 1 100.00
spi_device_tpm_sts_read 1.250s 63.822us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 33.550s 14861.105us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 12.370s 21410.662us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.960s 258.685us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.960s 258.685us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.950s 916.871us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.950s 916.871us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.950s 916.871us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.950s 916.871us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.950s 916.871us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.760s 469.581us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 15.710s 3714.449us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 15.710s 3714.449us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 15.710s 3714.449us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.100s 160.933us 1 1 100.00
spi_device_read_buffer_direct 3.800s 766.547us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 15.710s 3714.449us 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 118.680s 52663.113us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.880s 127.596us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.880s 127.596us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 47.410s 3551.443us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 328.800s 50654.212us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 56.740s 56994.172us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.110s 18.707us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.040s 146.256us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.140s 178.187us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.140s 178.187us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.510s 167.433us 1 1 100.00
spi_device_csr_rw 2.450s 289.877us 1 1 100.00
spi_device_csr_aliasing 6.230s 1255.814us 1 1 100.00
spi_device_same_csr_outstanding 4.320s 151.053us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.510s 167.433us 1 1 100.00
spi_device_csr_rw 2.450s 289.877us 1 1 100.00
spi_device_csr_aliasing 6.230s 1255.814us 1 1 100.00
spi_device_same_csr_outstanding 4.320s 151.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.670s 114.678us 1 1 100.00
spi_device_tl_intg_err 15.330s 710.424us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.330s 710.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 236.350s 154392.931us 1 1 100.00