Simulation Results: spi_host

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.97 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 37.000s 3597.751us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.103us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 20.073us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 376.584us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 78.099us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 38.831us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 20.073us 1 1 100.00
spi_host_csr_aliasing 1.000s 78.099us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.177us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 40.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 23.087us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 39.536us 1 1 100.00
spi_host_error_cmd 1.000s 48.092us 1 1 100.00
spi_host_event 6.000s 1279.886us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 85.600us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 85.600us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 85.600us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 11.000s 448.193us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 71.140us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 85.600us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 85.600us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 37.000s 3597.751us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 37.000s 3597.751us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 54.000s 1546.845us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 184.988us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 48.000s 12500.453us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 49.638us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 39.536us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 34.354us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 15.923us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 122.091us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 122.091us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.103us 1 1 100.00
spi_host_csr_rw 2.000s 20.073us 1 1 100.00
spi_host_csr_aliasing 1.000s 78.099us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 30.574us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.103us 1 1 100.00
spi_host_csr_rw 2.000s 20.073us 1 1 100.00
spi_host_csr_aliasing 1.000s 78.099us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 30.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 99.431us 1 1 100.00
spi_host_sec_cm 2.000s 244.487us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 99.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 283.000s 11545.624us 1 1 100.00