Simulation Results: sram_ctrl/main

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.98 %
  • code
  • 96.81 %
  • assert
  • 96.32 %
  • func
  • 91.80 %
  • block
  • 96.08 %
  • line
  • 96.81 %
  • branch
  • 94.33 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 1320.533us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 12.821us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 85.476us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 254.887us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.668us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1387.570us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 85.476us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.668us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 144.000s 21138.956us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 128.000s 23203.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 5668.304us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 72.000s 2578.567us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 173.000s 39689.578us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 33.000s 5209.203us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 61.000s 84037.758us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 26.000s 31873.262us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 8.000s 2898.703us 1 1 100.00
sram_ctrl_partial_access_b2b 196.000s 86012.074us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 5541.339us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 2892.838us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2798.756us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 14.000s 1685.240us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 360.682us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 74.000s 30136.827us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 18.521us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 204.816us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 204.816us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 12.821us 1 1 100.00
sram_ctrl_csr_rw 1.000s 85.476us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.668us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.749us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 12.821us 1 1 100.00
sram_ctrl_csr_rw 1.000s 85.476us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.668us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 7240.458us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 211.670us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 115.904us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 211.670us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 115.904us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 1685.240us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 1685.240us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 85.476us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 26.000s 31873.262us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 31873.262us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 31873.262us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 61.000s 84037.758us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 674.866us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 7240.458us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 2376.614us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 1320.533us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 1320.533us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 26.000s 31873.262us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 211.670us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 61.000s 84037.758us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 211.670us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 211.670us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 1320.533us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 211.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 38.000s 3548.996us 1 1 100.00