Simulation Results: sram_ctrl/ret

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.19 %
  • code
  • 83.33 %
  • assert
  • 96.43 %
  • func
  • 93.80 %
  • block
  • 93.73 %
  • line
  • 94.89 %
  • branch
  • 89.51 %
  • toggle
  • 82.23 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 60.870us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 19.195us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.937us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 110.995us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.788us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 58.432us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.937us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.788us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 93.720us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 287.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 12.000s 2330.515us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 176.000s 11919.679us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 410.647us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 1576.932us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.000s 111.684us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 2389.944us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 55.579us 1 1 100.00
sram_ctrl_partial_access_b2b 188.000s 42959.351us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 66.516us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 140.449us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 281.443us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 301.107us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 47.484us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 29.000s 1387.921us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.478us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 125.807us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 125.807us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.195us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.937us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.788us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 32.909us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.195us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.937us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.788us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 32.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 480.254us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 660.284us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 198.743us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 660.284us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 198.743us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 301.107us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 301.107us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.937us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2389.944us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2389.944us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2389.944us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.000s 111.684us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 34.870us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 480.254us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 74.035us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 60.870us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 60.870us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 2389.944us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 660.284us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.000s 111.684us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 660.284us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 660.284us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 60.870us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 660.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.000s 891.922us 1 1 100.00