Simulation Results: sysrst_ctrl

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.18 %
  • code
  • 93.49 %
  • assert
  • 95.02 %
  • func
  • 70.04 %
  • line
  • 97.73 %
  • branch
  • 97.52 %
  • cond
  • 95.94 %
  • toggle
  • 100.00 %
  • FSM
  • 76.28 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.550s 2129.639us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.090s 2490.290us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.530s 2512.643us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.750s 2532.323us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.880s 4034.909us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 8.800s 2063.600us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 21.460s 51564.009us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.120s 2743.747us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 8.430s 2067.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 8.800s 2063.600us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.120s 2743.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 62.700s 141310.240us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 64.610s 171717.457us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 19.870s 15913.042us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 8.100s 5629.996us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.170s 2545.517us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 6.450s 2077.718us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.320s 2889.676us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.970s 2634.291us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 8.510s 9778.385us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 21.270s 36949.147us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 101.550s 559946.643us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.830s 2034.380us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 5.840s 2012.029us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 7.990s 2035.425us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 7.990s 2035.425us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.880s 4034.909us 1 1 100.00
sysrst_ctrl_csr_rw 8.800s 2063.600us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.120s 2743.747us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.080s 5144.368us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.880s 4034.909us 1 1 100.00
sysrst_ctrl_csr_rw 8.800s 2063.600us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.120s 2743.747us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.080s 5144.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 53.210s 22013.965us 1 1 100.00
sysrst_ctrl_tl_intg_err 20.190s 22441.427us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 20.190s 22441.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 14.960s 5144.939us 1 1 100.00